An AES encryption and decryption project that follows SPI (Serial Peripheral Interface) specification. Implemented in Verilog
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May 19, 2023 - Verilog
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logic-design
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This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, SystemVerilog, and SVA. The main objectives included designing modules compliant with industry standards such as APB (Advanced Peripheral Bus), memory systems, and systolic matrix multiplication.
verification matrix-multiplication verilog systemverilog questasim logic-design sva systolic-arrays amba-apb functional-coverage chip-design
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Jun 26, 2024 - Verilog
This repo is for my IEEE ASU Student Branch Digital IC Design workshop, an introduction to digital design using Verilog, this is a documentation of my tasks.
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Oct 10, 2023 - Verilog
Combinational Multiplier Using verilog
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May 14, 2021 - Verilog
Carry Select Adder Using verilog
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May 14, 2021 - Verilog
A digital design for the SPI protocol, delivered as a project for the logic design course
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May 14, 2021 - Verilog
A carry select adder is an arithmetic combinational logic circuit which adds two N- bit binary numbers and outputs their N-bit binary sum and a 1-bit carry.
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Aug 9, 2020 - Verilog
this is a college project of making SPI interface using verilog
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Jun 8, 2022 - Verilog
Implementation of Texas Hold'em Poker on Verilog(Basys3 FGPA)
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May 11, 2024 - Verilog
Verilog programs in gate level, dataflow & behavioural modelling with testbenches written in intel FPGA tested with ModelSim simulator
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Feb 21, 2024 - Verilog
VARILAG LAGIK
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Dec 8, 2020 - Verilog
EECS207001
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Jan 22, 2023 - Verilog
A Verilog-based implementation of a 2-bit Ripple Carry Adder with a comprehensive testbench for functional verification, ideal for beginners exploring digital design and HDL concepts. 🚀
open-source simulation verilog icarus-verilog gtkwave vlsi adder digital-design logic-design 2-bit ripple-carry-adder
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Jan 4, 2025 - Verilog
Created AMD-Am2901 chip clone (4-bit ALU) with Cadence Virtuoso from a transistor level, manually creating datapath and generating control via CAD. Skills employed: Cadence Virtuoso, Logic (VLSI) Design, Verilog
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Jul 2, 2023 - Verilog
MK-LMC SIGANFU Tactical Power Armor - Final Verilog Project of Logic Design
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Mar 22, 2023 - Verilog
modelled encryption-decryption module using verilog. Given a text file, it can be encrypted using encryptor and can be decrypted later using decryptor.
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Dec 7, 2021 - Verilog
Using a linear feedback shift register (LFSR), design a pseudorandom binary sequence (PRBS) generator.
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Aug 9, 2020 - Verilog
11020EECS101002
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Sep 11, 2022 - Verilog
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