2019 International Conference on Signal, Control and Communication (SCC), 2019
This paper presents an approach based on a top-down design methodology that is used to design a v... more This paper presents an approach based on a top-down design methodology that is used to design a voltage-controlled oscillator based on behavioral modeling.Our strategy consists of creating a synthesis technique traducing a voltage-controlled oscillator VHDL-AMS description into a well-matched transistor level.The methodology uses several computer-aided design tools and a lot of transistor-level simulations are achieved to validate the efficiency of the proposed models.This method aims to guide designer through the project process from specification to transistor level parameters dimensioning without an expertise necessity.
In this paper, an optimization method using "experience plan" is applied to optimize a fractional... more In this paper, an optimization method using "experience plan" is applied to optimize a fractional-N frequency synthesizer's performances for wireless systems. The "experience plan" is applied on a VHDLAMS description using seven parameters having in view to minimize the loop response time and the synthesizer output frequency.
Aeu-international Journal of Electronics and Communications, 2007
In this study, we expose new approaches to design and optimize systems at a high level descriptio... more In this study, we expose new approaches to design and optimize systems at a high level description using Very High Speed Integrated Circuit Hardware Description Language for Analog and Mixed Systems (VHDL-AMS) standard. We detail a theoretical approach to develop self-tuned ...
2019 International Conference on Signal, Control and Communication (SCC), 2019
This paper presents an approach based on a top-down design methodology that is used to design a v... more This paper presents an approach based on a top-down design methodology that is used to design a voltage-controlled oscillator based on behavioral modeling.Our strategy consists of creating a synthesis technique traducing a voltage-controlled oscillator VHDL-AMS description into a well-matched transistor level.The methodology uses several computer-aided design tools and a lot of transistor-level simulations are achieved to validate the efficiency of the proposed models.This method aims to guide designer through the project process from specification to transistor level parameters dimensioning without an expertise necessity.
In this paper, an optimization method using "experience plan" is applied to optimize a fractional... more In this paper, an optimization method using "experience plan" is applied to optimize a fractional-N frequency synthesizer's performances for wireless systems. The "experience plan" is applied on a VHDLAMS description using seven parameters having in view to minimize the loop response time and the synthesizer output frequency.
Aeu-international Journal of Electronics and Communications, 2007
In this study, we expose new approaches to design and optimize systems at a high level descriptio... more In this study, we expose new approaches to design and optimize systems at a high level description using Very High Speed Integrated Circuit Hardware Description Language for Analog and Mixed Systems (VHDL-AMS) standard. We detail a theoretical approach to develop self-tuned ...
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Papers by SONIA ELOUED