High-Bitrate-Measurement-System-Oriented Lower-Jitter 113-Gbit/s 2:1 Multiplexer and 1:2 Demultiplexer Modules Using 1-µm InP/InGaAs/InP Double Heterojunction Bipolar Transistors

Yutaka ARAYASHIKI; Takashi KAMIZONO; Yukio OHKUBO; Taisuke MATSUMOTO; Yoshiaki AMANO; Yutaka MATSUOKA

doi:10.1587/transele.E96.C.912

Special Section on Analog Circuits and Related SoC Integration Technologies

High-Bitrate-Measurement-System-Oriented Lower-Jitter 113-Gbit/s 2:1 Multiplexer and 1:2 Demultiplexer Modules Using 1-µm InP/InGaAs/InP Double Heterojunction Bipolar Transistors

Yutaka ARAYASHIKI, Takashi KAMIZONO, Yukio OHKUBO, Taisuke MATSUMOTO, Yoshiaki AMANO, Yutaka MATSUOKA

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Keywords: DHBT, MUX, DEMUX, G-CPW, module

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2013 Volume E96.C Issue 6 Pages 912-919

DOI https://doi.org/10.1587/transele.E96.C.912

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Abstract

We fabricated low-jitter 2:1 multiplexer (MUX) and 1:2 demultiplexer (DEMUX) modules for bit error rate testers that can be used for research into ultra-high-bitrate communication subsystems and devices with bitrates of over 100Gbit/s. The 1:2 DEMUX IC design took into consideration an IC layout allowing module pin placement for optimal utility. With regard to mounting, the 2:1 MUX and 1:2 DEMUX modules were constructed using transmission lines of grounded coplanar waveguide (G-CPW) configuration, which offers excellent high-frequency characteristics. These modules operated at 113Gbit/s with a low root mean square jitter of 548fs and 587fs, respectively.

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