A 0.9 V 2.72 µW 200 kS/s SAR ADC with ladder-based time-domain comparator

Xiaolin Yang; Yin Zhou; Lihan Tang; Yangtao Dong; Menglian Zhao; Lin Deng; Xiaobo Wu; Xiaolei Zhu

doi:10.1587/elex.14.20170003

LETTER

A 0.9 V 2.72 µW 200 kS/s SAR ADC with ladder-based time-domain comparator

Xiaolin Yang, Yin Zhou, Lihan Tang, Yangtao Dong, Menglian Zhao, Lin Deng, Xiaobo Wu, Xiaolei Zhu

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Keywords: bio-medical devices, SAR ADC, time-domain comparator

JOURNAL FREE ACCESS

2017 Volume 14 Issue 5 Pages 20170003

DOI https://doi.org/10.1587/elex.14.20170003

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Abstract

This paper presents a 200 kS/s 12-bit successive approximation ADC with a new ladder-based time-domain comparator. The proposed comparator utilizes differential multi-ladder stages, resulting in improvement of gain and noise performance. The chip is designed and fabricated in a standard 0.18 µm CMOS technology with area of 0.127 mm². With a supply of 0.9 V, the ADC consumes 2.72 µW at the sampling rate of 200 kS/s. The measured SNDR and SFDR are 61.6 dB and 66.1 dB respectively, providing an ENOB of 9.9 bits, and the corresponding FOM of 28 fJ/conv-step.

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