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Architectural improvements for data-driven VLSI processing arrays

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Shlomit Weiss,

Ilan Spillinger,

Gabriel M. SibermanAuthors Info & Claims

FPCA '89: Proceedings of the fourth international conference on Functional programming languages and computer architecture

Pages 243 - 259

https://doi.org/10.1145/99370.99389

Published: 01 November 1989 Publication History

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[1]

I. Korcn, B. Mendelson, I. Peled, and G.M. Silberman, "A Data-Driven VLSI Array for Arbium'y Algorithms," IEEE Computer, Vol. 21, No. 10, October 1988, pp. 30-43.

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Google Scholar

[2]

J.R. McGraw, "The VAL Language: Description and Analysis,~ ACM Trans. on Prog. Lang. and Systems, Vol. 4, No. 1, $anuary 1982, pp. 44-82.

Digital Library

Google Scholar

[3]

B. Mcndelson and G.M. Silberman, ~Mapping Data Flow Programs on a VLSI Array of Processors," Proc. 2987 Int'l Conf. Computer Architecture, June 1987, pp. 72-80.

Digital Library

Google Scholar

[4]

I. P~lcd, A Data-Driven Processing Element, M.$c. Thesis (in Hebrew), Dept. of Electrical Engineering, Technion, 1986.

Google Scholar

[5]

E.M. Reingold, J. Nicvergelt, and N. De, o, Combinatorial Algorithms: Theory and Practice, Prentice- Hall, Englewood Cliffs, New Jersey, 1977.

Digital Library

Google Scholar

[6]

Y. Perl and M. Snir, "Circuit Partitioning with Size and Connection Constraints," NE7~ORKS, Vol. 13, 1983, pp. 365-375.

Google Scholar

[7]

B. Krishnamurthy, "An Improved Min-Cut Algorithm For Partitioning VLSi Networks," IEEE Trans. on Computers, Vol. C-33, No.5, May 1984, pp. 438446.

Google Scholar

[8]

J. Pearl, Heuristics: Intelligent Search Strategies for Computer Problem Solving, Addison-Wesley, Reading, Massachusetts, 1984.

Digital Library

Google Scholar

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Robič BŠilc J(2005)High-performance computing on a honeycomb architectureParallel Computation10.1007/3-540-57314-3_1(1-13)Online publication date: 29-May-2005
https://doi.org/10.1007/3-540-57314-3_1
Robic BSilc JBlaznik PKolbezen P(1991)On reducing the dataflow-graph hosting area[1991] Proceedings, Advanced Computer Technology, Reliable Systems and Applications10.1109/CMPEUR.1991.257371(138-142)Online publication date: 1991
https://doi.org/10.1109/CMPEUR.1991.257371
Vasell JVasell J(1991)The Function Processor: An Architecture for Efficient Execution of Recursive FunctionsParle ’91 Parallel Architectures and Languages Europe10.1007/978-3-662-25209-3_8(101-118)Online publication date: 1991
https://doi.org/10.1007/978-3-662-25209-3_8

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Architectural improvements for data-driven VLSI processing arrays

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FPCA '89: Proceedings of the fourth international conference on Functional programming languages and computer architecture

November 1989

395 pages

ISBN:0897913280

DOI:10.1145/99370

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Joseph E. Stoy

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 November 1989

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FPCA89: The International Conference on Functional Programming Languages & Computer Architectures

September 11 - 13, 1989

Imperial College, London, United Kingdom

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Robič BŠilc J(2005)High-performance computing on a honeycomb architectureParallel Computation10.1007/3-540-57314-3_1(1-13)Online publication date: 29-May-2005
https://doi.org/10.1007/3-540-57314-3_1
Robic BSilc JBlaznik PKolbezen P(1991)On reducing the dataflow-graph hosting area[1991] Proceedings, Advanced Computer Technology, Reliable Systems and Applications10.1109/CMPEUR.1991.257371(138-142)Online publication date: 1991
https://doi.org/10.1109/CMPEUR.1991.257371
Vasell JVasell J(1991)The Function Processor: An Architecture for Efficient Execution of Recursive FunctionsParle ’91 Parallel Architectures and Languages Europe10.1007/978-3-662-25209-3_8(101-118)Online publication date: 1991
https://doi.org/10.1007/978-3-662-25209-3_8

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Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs

Algorithms and methodologies for routability-driven vlsi placement

An architectural exploration of via patterned gate arrays

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Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs

Algorithms and methodologies for routability-driven vlsi placement

An architectural exploration of via patterned gate arrays

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