SHAPER: synthesis for hybrid FPGA architectures containing PLA elements using reconvergence analysis

This paper discusses the technology mapping problem on Hybrid Field Programmable Architectures (HFPA). HFPAs are realized using a combination of the following programmable logic devices, namely, Lookup Tables (LUTs) and Programmable Logic Arrays (PLAs). The HPFAs provide the designers with the advantages of both LUT-based Field Programmable Gate Arrays and PLAs. Specifically, use of PLAs can result in reduction of area required for mapping a circuit. Designing a methodology that maps a given circuit on to the HFPA that exploits the above-mentioned advantages to the maximum is a problem of very great research and commercial interest. This paper presents the SHAPER, which maps the circuits onto HFPAs using reconvergence analysis. Empirically, it is shown that SHAPER yields 18% better area-reduction than the previous known algorithms.