Article

Energy characterization of a tiled architecture processor with on-chip networks

Authors:

Jason Sungtae Kim,

Michael Bedford Taylor,

Jason Miller,

David WentzlaffAuthors Info & Claims

ISLPED '03: Proceedings of the 2003 international symposium on Low power electronics and design

Pages 424 - 427

https://doi.org/10.1145/871506.871610

Published: 25 August 2003 Publication History

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Abstract

Tiled architectures provide a paradigm for designers to turn silicon resources into processors with burgeoning quantities of programmable functional units and memories. The architecture has a dual responsibility: first, it must expose these resources in a way that is programmable. Second, it needs to manage the power associated with such resources.We present the power management facilities of the 16-tile Raw microprocessor. This design selectively turns on and off 48 SRAM macros, 96 functional unit clusters, 32 fetch units, and over 250 unique processor pipeline stages, all according to the needs of the computation and environment at hand.

References

[1]

Michael Taylor et al. The Raw Microprocessor. IEEE Micro, Apr 2002.

Google Scholar

[2]

R. Ho, K. Mai, M. Horowitz. Efficient On-Chip Global Interconnects. IEEE Symposium on VLSI Circuits, June 2003.

Google Scholar

[3]

Michael Taylor et al. Scalar Operand Networks: On-chip Interconnect for ILP in Partitioned Architectures. Proc. HPCA, Feb 2003.

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[4]

H. Wang, et al. Power Model for Routers. IEEE Micro, Jan 2003.

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[5]

Gunther, et al. Managing the Impact of Increasing Microprocessor Power Consumption. Intel Technology Journal. 1Q2001.

Google Scholar

[6]

Walter Lee, et al. Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine. Proc. ASPLOS, 1998.

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Index Terms

Energy characterization of a tiled architecture processor with on-chip networks
1. Computer systems organization
  1. Architectures
    1. Distributed architectures

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Published In

ISLPED '03: Proceedings of the 2003 international symposium on Low power electronics and design

August 2003

502 pages

ISBN:158113682X

DOI:10.1145/871506

General Chairs:
Ingrid Verbauwhede
University of California, Los Angeles, CA
,
Hyung Roh
Samsung Electronics

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 25 August 2003

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ISLPED03: International Symposium on Low Power Electronics and Design

August 25 - 27, 2003

Seoul, Korea

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ISLPED '03 Paper Acceptance Rate 90 of 221 submissions, 41%;

Overall Acceptance Rate 398 of 1,159 submissions, 34%

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https://doi.org/10.1142/S0218126625500379
Ouyang YChen ZXu DLiang H(2024)SPONGE+: A NoC-based power gating scheme for overall router column opening and closing controlMicroelectronics Journal10.1016/j.mejo.2024.106234149(106234)Online publication date: Jul-2024
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The Superthreaded Processor Architecture

A design of EPIC type processor based on MIPS architecture

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The Superthreaded Processor Architecture

A design of EPIC type processor based on MIPS architecture

A Front-end Execution Architecture for High Energy Efficiency

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