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Very Long Instruction Word architectures and the ELI-512

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Joseph A. FisherAuthors Info & Claims

ISCA '83: Proceedings of the 10th annual international symposium on Computer architecture

Pages 140 - 150

https://doi.org/10.1145/800046.801649

Published: 13 June 1983 Publication History

Abstract

By compiling ordinary scientific applications programs with a radical technique called trace scheduling, we are generating code for a parallel machine that will run these programs faster than an equivalent sequential machine—we expect 10 to 30 times faster.

Trace scheduling generates code for machines called Very Long Instruction Word architectures. In Very Long Instruction Word machines, many statically scheduled, tightly coupled, fine-grained operations execute in parallel within a single instruction stream. VLIWs are more parallel extensions of several current architectures.

These current architectures have never cracked a fundamental barrier. The speedup they get from parallelism is never more than a factor of 2 to 3. Not that we couldn't build more parallel machines of this type; but until trace scheduling we didn't know how to generate code for them. Trace scheduling finds sufficient parallelism in ordinary code to justify thinking about a highly parallel VLIW.

At Yale we are actually building one. Our machine, the ELI-512, has a horizontal instruction word of over 500 bits and will do 10 to 30 RISC-level operations per cycle [Patterson 82]. ELI stands for Enormously Longword Instructions; 512 is the size of the instruction word we hope to achieve. (The current design has a 1200-bit instruction word.)

Once it became clear that we could actually compile code for a VLIW machine, some new questions appeared, and answers are presented in this paper. How do we put enough tests in each cycle without making the machine too big? How do we put enough memory references in each cycle without making the machine too slow?

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Index Terms

Very Long Instruction Word architectures and the ELI-512
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Very long instruction word
    2. Serial architectures
      1. Complex instruction set computing
      2. Reduced instruction set computing

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cover image ACM Conferences

ISCA '83: Proceedings of the 10th annual international symposium on Computer architecture

June 1983

424 pages

ISBN:0897911016

DOI:10.1145/800046

ACM SIGARCH Computer Architecture News Volume 11, Issue 3
June 1983
413 pages
ISSN:0163-5964
DOI:10.1145/1067651
Issue’s Table of Contents

Copyright © 1983 Author.

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SIGARCH: ACM Special Interest Group on Computer Architecture
IEEE-CS: Computer Society

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 13 June 1983

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