Article

Optimizing indirect branch prediction accuracy in virtual machine interpreters

Authors:

David GreggAuthors Info & Claims

PLDI '03: Proceedings of the ACM SIGPLAN 2003 conference on Programming language design and implementation

Pages 278 - 288

https://doi.org/10.1145/781131.781162

Published: 09 May 2003 Publication History

Abstract

Interpreters designed for efficiency execute a huge number of indirect branches and can spend more than half of the execution time in indirect branch mispredictions. Branch target buffers are the best widely available form of indirect branch prediction; however, their prediction accuracy for existing interpreters is only 2%--50%. In this paper we investigate two methods for improving the prediction accuracy of BTBs for interpreters: replicating virtual machine (VM) instructions and combining sequences of VM instructions into superinstructions. We investigate static (interpreter build-time) and dynamic (interpreter run-time) variants of these techniques and compare them and several combinations of these techniques. These techniques can eliminate nearly all of the dispatch branch mispredictions, and have other benefits, resulting in speedups by a factor of up to 3.17 over efficient threaded-code interpreters, and speedups by a factor of up to 1.3 over techniques relying on superinstructions alone.

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Polito GPalumbo NLabsari SDucasse STesone P(2022)Interpreter Register Autolocalisation: Improving the Performance of Efficient InterpretersCompanion Proceedings of the 6th International Conference on the Art, Science, and Engineering of Programming10.1145/3532512.3532518(1-5)Online publication date: 21-Mar-2022
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Misse-Chanabier PPolito GDucasse SBouraqadi NFabresse LTesone PHong JBures MPark JCerny T(2022)Differential testing of simulation-based VM generatorsProceedings of the 37th ACM/SIGAPP Symposium on Applied Computing10.1145/3477314.3507171(1280-1283)Online publication date: 25-Apr-2022
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Index Terms

Optimizing indirect branch prediction accuracy in virtual machine interpreters
1. Software and its engineering
  1. Software notations and tools
    1. Compilers
      1. Interpreters
    2. General programming languages

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Reviews

Reviewer: Soundararajan Ezekiel

Ertl and Gregg investigate two methods for improving the prediction accuracy of branch target buffers: virtual machine instruction and combining sequences of virtual machine instruction into super instructions. They investigate combinations of the static and dynamic variants of each technique. By studying various performance monitoring counters, such as cycles, instructions, taken instructions, taken branch instructions that are mispredicted, instruction fetch misses, code bytes, and miss cycles, the authors claim their method eliminates most dispatch branch mispredictions, and increases the speed to 3.17 times faster than standard threaded-code interpreters. This paper is very well researched and written. Online Computing Reviews Service

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Published In

cover image ACM Conferences

PLDI '03: Proceedings of the ACM SIGPLAN 2003 conference on Programming language design and implementation

June 2003

360 pages

ISBN:1581136625

DOI:10.1145/781131

General Chair:
Ron Cytron
Washington University, USA
,
Program Chair:
Rajiv Gupta
University of Arizona, USA

ACM SIGPLAN Notices Volume 38, Issue 5
May 2003
349 pages
ISSN:0362-1340
EISSN:1558-1160
DOI:10.1145/780822
Issue’s Table of Contents

Copyright © 2003 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 09 May 2003

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PLDI03: ACM SIGPLAN Conference on Programming Language Design and Implementation

June 9 - 11, 2003

California, San Diego, USA

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PLDI '03 Paper Acceptance Rate 28 of 131 submissions, 21%;

Overall Acceptance Rate 406 of 2,067 submissions, 20%

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Cited By

Zhang QXu LXu B(2022)RegCPython: A Register-based Python Interpreter for Better PerformanceACM Transactions on Architecture and Code Optimization10.1145/356897320:1(1-25)Online publication date: 16-Dec-2022
https://dl.acm.org/doi/10.1145/3568973
Polito GPalumbo NLabsari SDucasse STesone P(2022)Interpreter Register Autolocalisation: Improving the Performance of Efficient InterpretersCompanion Proceedings of the 6th International Conference on the Art, Science, and Engineering of Programming10.1145/3532512.3532518(1-5)Online publication date: 21-Mar-2022
https://dl.acm.org/doi/10.1145/3532512.3532518
Misse-Chanabier PPolito GDucasse SBouraqadi NFabresse LTesone PHong JBures MPark JCerny T(2022)Differential testing of simulation-based VM generatorsProceedings of the 37th ACM/SIGAPP Symposium on Applied Computing10.1145/3477314.3507171(1280-1283)Online publication date: 25-Apr-2022
https://dl.acm.org/doi/10.1145/3477314.3507171
Zhang QXu LZhang XXu B(2022)Quantifying the interpretation overhead of PythonScience of Computer Programming10.1016/j.scico.2021.102759215:COnline publication date: 1-Mar-2022
https://dl.acm.org/doi/10.1016/j.scico.2021.102759
Kiriansky VXu HRinard MAmarasinghe SEvripidou SStenström PO'Boyle M(2018)Cimple: instruction and memory level parallelismProceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques10.1145/3243176.3243185(1-16)Online publication date: 1-Nov-2018
https://dl.acm.org/doi/10.1145/3243176.3243185
Kim CKim SCho HKim DKim JOh YJang HLee J(2016)Short-circuit dispatchACM SIGARCH Computer Architecture News10.1145/3007787.300116844:3(291-303)Online publication date: 18-Jun-2016
https://dl.acm.org/doi/10.1145/3007787.3001168
Kim CKim SCho HKim DKim JOh YJang HLee JMin SLoh G(2016)Short-circuit dispatchProceedings of the 43rd International Symposium on Computer Architecture10.1109/ISCA.2016.34(291-303)Online publication date: 18-Jun-2016
https://dl.acm.org/doi/10.1109/ISCA.2016.34
Rohou ESwamy BSeznec AOlukotun KSmith AHundt RMars J(2015)Branch prediction and the performance of interpretersProceedings of the 13th Annual IEEE/ACM International Symposium on Code Generation and Optimization10.5555/2738600.2738614(103-114)Online publication date: 7-Feb-2015
https://dl.acm.org/doi/10.5555/2738600.2738614
Rohou ESwamy BSeznec A(2015)Branch prediction and the performance of interpreters — Don't trust folklore2015 IEEE/ACM International Symposium on Code Generation and Optimization (CGO)10.1109/CGO.2015.7054191(103-114)Online publication date: Feb-2015
https://doi.org/10.1109/CGO.2015.7054191
Savrun-Yeniçeri GZhang WZhang HSeckler ELi CBrunthaler SLarsen PFranz M(2014)Efficient hosted interpreters on the JVMACM Transactions on Architecture and Code Optimization10.1145/253264211:1(1-24)Online publication date: 1-Feb-2014
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