Article

An architectural exploration of via patterned gate arrays

Authors:

Chetan Patel,

Anthony Cozzie,

Herman Schmit,

Larry PileggiAuthors Info & Claims

ISPD '03: Proceedings of the 2003 international symposium on Physical design

Pages 184 - 189

https://doi.org/10.1145/640000.640039

Published: 06 April 2003 Publication History

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Abstract

In this work we investigate the architecture of a Via Patterned Gate Array (VPGA) [1], focusing primarily on: 1) the optimal lookup table (LUT) size; and 2) a comparison the crossbar and switch block routing architectures. Unlike FPGAs, the routing architectures in a VPGA do not dominate the total area of the circuit. Therefore our results suggest that using smaller LUTs results in a much faster and smaller design. In the routing architecture comparison, our results also show that the switch block architecture is inferior to the crossbar architecture in terms of area utilization. As the number of routing tracks grows, the switch block architecture begins to dominate the total area of the design as in the case of the FPGAs.

References

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Cited By

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Cho MChoudhury MPuri RRen HXiang HNam GMo FBrayton R(2016)Structured Digital DesignElectronic Design Automation for IC Implementation, Circuit Design, and Process Technology10.1201/b19714-9(155-182)Online publication date: 14-Apr-2016
https://doi.org/10.1201/b19714-9
Dupuis SNoury LFel N(2014)A regular fabric design methodology for applications requiring specific layout-level design rulesMicroelectronics Journal10.1016/j.mejo.2013.11.00245:2(217-225)Online publication date: 1-Feb-2014
https://dl.acm.org/doi/10.1016/j.mejo.2013.11.002
Tsai MHsu PLi HHung YLiu Y(2013)Routability optimization for crossbar-switch structured ASIC designACM Transactions on Design Automation of Electronic Systems10.1145/2491477.249148318:3(1-28)Online publication date: 29-Jul-2013
https://dl.acm.org/doi/10.1145/2491477.2491483
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Index Terms

An architectural exploration of via patterned gate arrays
1. Hardware
  1. Very large scale integration design
    1. Application-specific VLSI designs

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Published In

ISPD '03: Proceedings of the 2003 international symposium on Physical design

April 2003

218 pages

ISBN:1581136501

DOI:10.1145/640000

General Chair:
Massoud Pedram
USC
,
Program Chair:
Charles J. Alpert
IBM

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 06 April 2003

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April 6 - 9, 2003

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Overall Acceptance Rate 62 of 172 submissions, 36%

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Cho MChoudhury MPuri RRen HXiang HNam GMo FBrayton R(2016)Structured Digital DesignElectronic Design Automation for IC Implementation, Circuit Design, and Process Technology10.1201/b19714-9(155-182)Online publication date: 14-Apr-2016
https://doi.org/10.1201/b19714-9
Dupuis SNoury LFel N(2014)A regular fabric design methodology for applications requiring specific layout-level design rulesMicroelectronics Journal10.1016/j.mejo.2013.11.00245:2(217-225)Online publication date: 1-Feb-2014
https://dl.acm.org/doi/10.1016/j.mejo.2013.11.002
Tsai MHsu PLi HHung YLiu Y(2013)Routability optimization for crossbar-switch structured ASIC designACM Transactions on Design Automation of Electronic Systems10.1145/2491477.249148318:3(1-28)Online publication date: 29-Jul-2013
https://dl.acm.org/doi/10.1145/2491477.2491483
Ho MAi YChau TYuen SChoy CLeong PPun K(2013)Architecture and design flow for a highly efficient structured ASICIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.219047821:3(424-433)Online publication date: 1-Mar-2013
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Tsung-Han Heish Rung-Bin Lin (2013)Via-configurable structured ASIC implementation of OpenRISC 1200 based SoC platform2013 International Symposium on Next-Generation Electronics10.1109/ISNE.2013.6512280(21-24)Online publication date: Mar-2013
https://doi.org/10.1109/ISNE.2013.6512280
Tung HLin RLi MHeish T(2012)Standard cell like via-configurable logic blocks for structured ASIC in an industrial design flowIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2011.217071220:12(2184-2197)Online publication date: 1-Dec-2012
https://dl.acm.org/doi/10.1109/TVLSI.2011.2170712
Noury LDupuis SFel N(2012)A reference low-complexity structured ASIC2012 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.2012.6271867(2709-2712)Online publication date: May-2012
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Chen SLin RTung HLin KDe Micheli GAl-Hashimi BMueller WMacii E(2010)Power gating design for standard-cell-like structured ASICsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871048(514-519)Online publication date: 8-Mar-2010
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Chen YPang HLin KLin RTung HSu SBahar RLombardi FAtienza DBrunvand E(2010)Via configurable three-input lookup-tables for structured ASICsProceedings of the 20th symposium on Great lakes symposium on VLSI10.1145/1785481.1785494(49-54)Online publication date: 16-May-2010
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Yi-Huang Hung Hung-Yi Li Po-Yang Hsu Yi-Yu Liu (2010)Dangling-wire avoidance routing for crossbar switch structured ASIC design styleProceedings of 2010 International Symposium on VLSI Design, Automation and Test10.1109/VDAT.2010.5496719(177-180)Online publication date: Apr-2010
https://doi.org/10.1109/VDAT.2010.5496719
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Enabling energy efficiency in via-patterned gate array devices

Embedded Design Using Programmable Gate Arrays

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