Article

A history-based I-cache for low-energy multimedia applications

Authors:

Koji Inoue,

V. G. Moshnyaga,

K. MurakamiAuthors Info & Claims

ISLPED '02: Proceedings of the 2002 international symposium on Low power electronics and design

Pages 148 - 153

https://doi.org/10.1145/566408.566447

Published: 12 August 2002 Publication History

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Abstract

This paper proposes a history-based tag-comparison scheme for reducing energy consumption of direct-mapped instruction caches. The proposed cache efficiently exploits program-execution footprints recorded in the Branch Target Buffer (BTB), and attempts to detect and eliminate unnecessary tag checks at run time. Simulation results show that our approach can eliminate up to 95% of tag checks, saving the cache energy by 17%, while affecting the processor performance by only 0.2%.

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Cited By

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Lee JKim SShanbhag NPoncino MChou PAmerasekera A(2012)Adopting TLB index-based tagging to data caches for tag energy reductionProceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design10.1145/2333660.2333716(231-236)Online publication date: 30-Jul-2012
https://dl.acm.org/doi/10.1145/2333660.2333716
Lee JHong SKim SChang NNakamura HInoue KOsada KPoncino M(2011)TLB index-based tagging for cache energy reductionProceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design10.5555/2016802.2016828(85-90)Online publication date: 1-Aug-2011
https://dl.acm.org/doi/10.5555/2016802.2016828
Lee JHong SKim S(2011)TLB index-based tagging for cache energy reductionIEEE/ACM International Symposium on Low Power Electronics and Design10.1109/ISLPED.2011.5993612(85-90)Online publication date: Aug-2011
https://doi.org/10.1109/ISLPED.2011.5993612
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Index Terms

A history-based I-cache for low-energy multimedia applications
1. Computer systems organization
  1. Architectures
2. Hardware
  1. Integrated circuits
    1. Semiconductor memory

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Published In

ISLPED '02: Proceedings of the 2002 international symposium on Low power electronics and design

August 2002

342 pages

ISBN:1581134754

DOI:10.1145/566408

General Chairs:
Vivek De
Intel Corporation
,
Mary Jane Irwin
Penn State University
,
Program Chairs:
Ingrid Verbauwhede
University of California, Los Angeles
,
Christian Piguet
CSEM

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 12 August 2002

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Conference

ISLPED02

Sponsor:

ISLPED02: International Symposium on Power Design and Electronics

August 12 - 14, 2002

California, Monterey, USA

Acceptance Rates

ISLPED '02 Paper Acceptance Rate 40 of 162 submissions, 25%;

Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

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Lee JKim SShanbhag NPoncino MChou PAmerasekera A(2012)Adopting TLB index-based tagging to data caches for tag energy reductionProceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design10.1145/2333660.2333716(231-236)Online publication date: 30-Jul-2012
https://dl.acm.org/doi/10.1145/2333660.2333716
Lee JHong SKim SChang NNakamura HInoue KOsada KPoncino M(2011)TLB index-based tagging for cache energy reductionProceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design10.5555/2016802.2016828(85-90)Online publication date: 1-Aug-2011
https://dl.acm.org/doi/10.5555/2016802.2016828
Lee JHong SKim S(2011)TLB index-based tagging for cache energy reductionIEEE/ACM International Symposium on Low Power Electronics and Design10.1109/ISLPED.2011.5993612(85-90)Online publication date: Aug-2011
https://doi.org/10.1109/ISLPED.2011.5993612
Artes ADuarte FAshouei MHuisken JAyala JAtienza DCatthoor F(2010)[2010] Energy Efficiency Using Loop Buffer based Instruction Memory OrganizationsProceedings of the 2010 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems10.1109/IWIA.2010.10(59-67)Online publication date: 17-Jan-2010
https://dl.acm.org/doi/10.1109/IWIA.2010.10
Ozturk OKandemir M(2008)ILP-Based energy minimization techniques for banked memoriesACM Transactions on Design Automation of Electronic Systems10.1145/1367045.136705913:3(1-40)Online publication date: 25-Jul-2008
https://dl.acm.org/doi/10.1145/1367045.1367059
Panda P(2007)Power Optimisation Strategies Targeting the Memory SubsystemDesigning Embedded Processors10.1007/978-1-4020-5869-1_6(131-155)Online publication date: 2007
https://doi.org/10.1007/978-1-4020-5869-1_6
Bouyssounouse BSifakis J(2005)Low power engineeringEmbedded Systems Design10.5555/2137690.2137724(450-478)Online publication date: 1-Jan-2005
https://dl.acm.org/doi/10.5555/2137690.2137724
Zhang YYang JVerbauwhede IRoh H(2003)Low cost instruction cache designs for tag comparison eliminationProceedings of the 2003 international symposium on Low power electronics and design10.1145/871506.871572(266-269)Online publication date: 25-Aug-2003
https://dl.acm.org/doi/10.1145/871506.871572

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