Article

Low-voltage memories for power-aware systems

Author:

Kiyoo ItohAuthors Info & Claims

ISLPED '02: Proceedings of the 2002 international symposium on Low power electronics and design

Pages 1 - 6

https://doi.org/10.1145/566408.566409

Published: 12 August 2002 Publication History

Abstract

This paper describes low-voltage RAM designs for stand-alone and embedded memories in terms of signal-to-noise-ratio designs of RAM cells and subthreshold-current reduction.First, structures and areas of current DRAM and SRAM cells are discussed. Next, low-voltage peripheral circuits that have been proposed so far are reviewed with focus on subthreshold-current reduction, speed variation, on-chip voltage conversion, and testing.Finally, based on the above discussion, a perspective is given with emphasis on needs for high-speed simple non-volatile RAMs, new devices/circuits for reducing active-mode leakage currents, and memory-rich SOC architectures.

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Cited By

(2018)Stand-By Power Reduction for SRAM MemoriesLow-Power Electronics Design10.1201/9781420039559-31(445-454)Online publication date: 3-Oct-2018
https://doi.org/10.1201/9781420039559-31
Cserveny SMasgonty JPiguet CPiguet C(2018)Stand-By Power Reduction For SRAM MemoriesLow-Power Processors and Systems on Chips10.1201/9781315220581-7(7-1-7-9)Online publication date: 3-Oct-2018
https://doi.org/10.1201/9781315220581-7
Kushwah CVishvakarma S(2012)Ultra-Low power sub-threshold SRAM cell design to improve read static noise marginProceedings of the 16th international conference on Progress in VLSI Design and Test10.1007/978-3-642-31494-0_16(139-146)Online publication date: 1-Jul-2012
https://dl.acm.org/doi/10.1007/978-3-642-31494-0_16
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Low-voltage memories for power-aware systems
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cover image ACM Conferences

ISLPED '02: Proceedings of the 2002 international symposium on Low power electronics and design

August 2002

342 pages

ISBN:1581134754

DOI:10.1145/566408

General Chairs:
Vivek De
Intel Corporation
,
Mary Jane Irwin
Penn State University
,
Program Chairs:
Ingrid Verbauwhede
University of California, Los Angeles
,
Christian Piguet
CSEM

Copyright © 2002 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 12 August 2002

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ISLPED02: International Symposium on Power Design and Electronics

August 12 - 14, 2002

California, Monterey, USA

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ISLPED '02 Paper Acceptance Rate 40 of 162 submissions, 25%;

Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

(2018)Stand-By Power Reduction for SRAM MemoriesLow-Power Electronics Design10.1201/9781420039559-31(445-454)Online publication date: 3-Oct-2018
https://doi.org/10.1201/9781420039559-31
Cserveny SMasgonty JPiguet CPiguet C(2018)Stand-By Power Reduction For SRAM MemoriesLow-Power Processors and Systems on Chips10.1201/9781315220581-7(7-1-7-9)Online publication date: 3-Oct-2018
https://doi.org/10.1201/9781315220581-7
Kushwah CVishvakarma S(2012)Ultra-Low power sub-threshold SRAM cell design to improve read static noise marginProceedings of the 16th international conference on Progress in VLSI Design and Test10.1007/978-3-642-31494-0_16(139-146)Online publication date: 1-Jul-2012
https://dl.acm.org/doi/10.1007/978-3-642-31494-0_16
Cserveny SMasgonty JPiguet C(2009)Stand-By Power Reduction for SRAM MemoriesLow-Power Processors and Systems on Chips10.1201/9781420037203.ch7(7-1-7-9)Online publication date: 4-Dec-2009
https://doi.org/10.1201/9781420037203.ch7
Marchal PCatthoor FBruni DBenini LGomez GPinuel L(2004)Integrated Task Scheduling and Data Assignment for SDRAMs in Dynamic ApplicationsIEEE Design & Test10.1109/MDT.2004.6621:5(378-387)Online publication date: 1-Sep-2004
https://dl.acm.org/doi/10.1109/MDT.2004.66
Marchal PGomez JPinuel LBruni DBenini LCatthoor FCorporaal H(2003)SDRAM-Energy-Aware Memory Allocation for Dynamic Multi-Media Applications on Multi-Processor PlatformsProceedings of the conference on Design, Automation and Test in Europe - Volume 110.5555/789083.1022779Online publication date: 3-Mar-2003
https://dl.acm.org/doi/10.5555/789083.1022779
Papanikolaou AMiranda MCatthoor FCorporaal HDe Man HDe Roest DStucchi MMaex KSylvester DStroobandt DScheffer LZarkesh-Ha P(2003)Global interconnect trade-off for technology over memory modules to application levelProceedings of the 2003 international workshop on System-level interconnect prediction10.1145/639929.639954(125-132)Online publication date: 5-Apr-2003
https://dl.acm.org/doi/10.1145/639929.639954

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