Article

Enhancing test efficiency for delay fault testing using multiple-clocked schemes

Authors:

Thomas W. WilliamsAuthors Info & Claims

DAC '02: Proceedings of the 39th annual Design Automation Conference

Pages 371 - 374

https://doi.org/10.1145/513918.514013

Published: 10 June 2002 Publication History

Get Access

Abstract

In conventional delay testing, the test clock is a single pre-defined parameter that is often set to be the same as the system clock. This paper discusses the potential of enhancing test efficiency by using multiple clock frequencies. The intuition behind our work is that for a given set of AC delay patterns, a carefully-selected, tighter clock would result in higher effectiveness to screen out the potential defective chips. Then, by using a smarter test clock scheme and combining with a second set of AC delay patterns, the overall quality of AC delay test can be enhanced while the cost of including the second pattern set can be minimized. We demonstrate these concepts through analysis and experiments using a statistical timing analysis framework with defect-injected simulation.

References

[1]

K. Baker, G. Gronthoud, M. Lousberg, I. Schanstra, and C. Hawkins. Defect Based Delay Testing of Resistive Vias-Contacts, A Critical Evaluation. Proceedings of IEEE International Test Conference, pages 467--476, September 1999.

Digital Library

Google Scholar

[2]

M. A. Breuer, C. Gleason, and S. Gupta. New Validation and Test Problems for High Performance Deep Sub-Micron VLSI Circuits. Tutorial Notes, IEEE VLSI Test Symposium, April 1997.

Digital Library

Google Scholar

[3]

J.-J. Liou, K.-T. Cheng, and D. Mukherjee. Path Selection for Delay Testing of Deep Sub-Micron Devices Using Statistical Performance Sensitivity Analysis. Proceedings of IEEE VLSI Test Symposium, pages 97--104, April 2000.

Digital Library

Google Scholar

[4]

J.-J. Liou, A. Krstić, K.-T. Cheng, D. Mukherjee, and S. Kundu. Performance Sensitivity Analysis Using Statistical Methods and Its Applications to Delay Testing. Proceedings of Asian South Pacific Design Automation Coneference, pages 587--592, January 2000.

Digital Library

Google Scholar

[5]

W. W. Mao and M. D. Ciletti. A Variable Observation Time Method for Testing Dlay Faults. Proceedings of Design Automation Conference, pages 728--731, June 1990.

Digital Library

Google Scholar

[6]

V. S. Iyengar and G. Vijayan. Optimized Test Application Timing for AC Test. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 11(11):1439--1449, November 1992.

Google Scholar

[7]

D. Dumas, P. Girard, C. Landrault, and S. Pravossoudovitch. Effectiveness of a Variable Sampling Time Strategy for Delay Fault Diagnosis. Proceedings of European Design and Test Conference, pages 518--523, March 1994.

Crossref

Google Scholar

[8]

W. B. Jone and Y. P. Ho. Delay Fault Coverage Enhancement Using Variable Observation Times. Journal of Electronic Testing: Theory and Applications, 11(2):131--146, October 1997.

Digital Library

Google Scholar

[9]

Anacad. Eldo v4.4.x User's Manual. 1996.

Google Scholar

[10]

N. N. Tendolkar. Analysis of Timing Failures Due to Random AC defects in VLSI moduels. Proceedings of Design Automation Conference, pages 709--714, June 1985.

Digital Library

Google Scholar

[11]

J. P. de~Gyvez. Integrated Circuits Defect-Sensitivity: Theory and Computational Models. Kluwer Academic Publishers, Boston, MA, 1993.

Crossref

Google Scholar

Cited By

View all

Li THuang SHsu HTzeng CHuang CLiou JMa HHuang PBor JTien CWang CWu C(2013)AC-plus scan methodology for small delay testing and characterizationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.218722321:2(329-341)Online publication date: 1-Feb-2013
https://dl.acm.org/doi/10.1109/TVLSI.2012.2187223
Lee BWang LAbadir MSentovich E(2006)Refined statistical static timing analysis throughProceedings of the 43rd annual Design Automation Conference10.1145/1146909.1146952(149-154)Online publication date: 24-Jul-2006
https://dl.acm.org/doi/10.1145/1146909.1146952
Júnior DRodriguez-Irago MSantos MTeixeira IVargas FTeixeira J(2005)Fault Modeling and Simulation of Power Supply Voltage Transients in Digital Systems on a ChipJournal of Electronic Testing: Theory and Applications10.1007/s10836-005-0972-z21:4(349-363)Online publication date: 1-Aug-2005
https://dl.acm.org/doi/10.1007/s10836-005-0972-z

Index Terms

Enhancing test efficiency for delay fault testing using multiple-clocked schemes
1. Hardware
  1. Hardware test
  2. Robustness

Recommendations

The Total Delay Fault Model and Statistical Delay Fault Coverage

Delay testing at the operational system clock rate can detect system timing failures caused by delay faults. However, delay fault coverage in terms of the percentage of the number of tested faults may not be an effective measure of delay testing. A ...
Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences

The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. In this context, it has been proven that Single Input Change (SIC) test ...
An optimized BIST test pattern generator for delay testing
VTS '97: Proceedings of the 15th IEEE VLSI Test Symposium

As delay testing using external testers requires expensive equipment, built-in self-test (BIST) is an alternative technique that can significantly reduce the test cost. In this paper, a BIST test pattern generator (TPG) design for the detection of delay ...

Comments

Information & Contributors

Information

Published In

DAC '02: Proceedings of the 39th annual Design Automation Conference

June 2002

956 pages

ISBN:1581134614

DOI:10.1145/513918

General Chair:
Bryan Ackland
Agere Systems, Inc., Holmdel, NJ

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 10 June 2002

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Article

Conference

DAC02

Sponsor:

SIGDA

DAC02: 39th Design Automation Conference

June 10 - 14, 2002

Louisiana, New Orleans, USA

Acceptance Rates

DAC '02 Paper Acceptance Rate 147 of 491 submissions, 30%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

3
Total Citations
View Citations
15
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 03 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

View all

Li THuang SHsu HTzeng CHuang CLiou JMa HHuang PBor JTien CWang CWu C(2013)AC-plus scan methodology for small delay testing and characterizationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.218722321:2(329-341)Online publication date: 1-Feb-2013
https://dl.acm.org/doi/10.1109/TVLSI.2012.2187223
Lee BWang LAbadir MSentovich E(2006)Refined statistical static timing analysis throughProceedings of the 43rd annual Design Automation Conference10.1145/1146909.1146952(149-154)Online publication date: 24-Jul-2006
https://dl.acm.org/doi/10.1145/1146909.1146952
Júnior DRodriguez-Irago MSantos MTeixeira IVargas FTeixeira J(2005)Fault Modeling and Simulation of Power Supply Voltage Transients in Digital Systems on a ChipJournal of Electronic Testing: Theory and Applications10.1007/s10836-005-0972-z21:4(349-363)Online publication date: 1-Aug-2005
https://dl.acm.org/doi/10.1007/s10836-005-0972-z

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

The Total Delay Fault Model and Statistical Delay Fault Coverage

Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences

An optimized BIST test pattern generator for delay testing

Comments

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Author Tags

Qualifiers

Conference

Acceptance Rates

Upcoming Conference

Other Metrics

Article Metrics

Other Metrics

Cited By

Login options

Full Access

PDF

eReader

Abstract

References

Cited By

Index Terms

Recommendations

The Total Delay Fault Model and Statistical Delay Fault Coverage

Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences

An optimized BIST test pattern generator for delay testing

Comments

Information

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Author Tags

Qualifiers

Conference

Acceptance Rates

Upcoming Conference

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

Login options

Full Access

View options

PDF

eReader

Figures

Other

Share

Share this Publication link

Share on social media

Affiliations