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A process cache memory for tightly coupled multiprocessor systems

Author:

Cosimo Antonio PreteAuthors Info & Claims

ACMSE '92: Proceedings of the 30th annual ACM Southeast Regional Conference

Pages 131 - 138

https://doi.org/10.1145/503720.503768

Published: 08 April 1992 Publication History

Abstract

Analysis of the simulation outputs and of the behaviour of some prototypes of shared-bus multiprocessors with cache memories showed that: (i) system performance depends on the percentage of write operations operating on shared copies and (ii) some events (such as process migration, execution of input/output interrupt routines on different processors, and so on) create a high number of shared copies derived from memory blocks belonging to private data of processes. Starting from these results, we have designed a new coherence protocol which works to reduce the number of shared copies. The basic new idea lies in (i) identifying the copies unused by the running process and (ii) destroying them when they are involved in shared-bus transactions. This paper describes this idea, the coherence protocol, the cache architecture requirements needed to realize such an idea.

References

[1]

Smith, A.J. Cache memories. ACM Computing Surveys, 14, 3, (1982) 473- 530.

Digital Library

[2]

Denning, P.J. On modeling program behaviour. In Proc. of the Spring Joint Computer Conference. AFIPS Press, Arlington, Va., 40, 0972), 937-944.

Digital Library

[3]

Satyanarayanan, M. Multiprocessors: A comparative study. Prentice-Hall, Englewood Cliffs, NJ., 1980.

[4]

Jones, A.K. and Schwarz, P. Experience using multiprocessor systems: A status report. Computing Surveys (ACM), 12, 2 (1980), 121-165.

Digital Library

[5]

Hwang, K. and Brigg, F.A. Computer architecture and parallel processing. McGRAW- Series in Computer Organization and Architecture, 1984.

Digital Library

[6]

Goodman, J.R. Cache memory optimization to reduce processer memory traffic. Journal of VLSI and Computer Systems 2, 1-2 (1987), 61-86.

Digital Library

[7]

Thakkar, P.G. and Shreekant G.F. The Balance multiprocessot system. 1EEE Micro 8, 1 (1988), 57-69.

Digital Library

[8]

Katz, R., Eggers, S., Wood, D.A., Perkins, C. and Sheldon, R.G. Implementing a cache consistency protocol. In Proc. of the 12th Int. Syrup. on Computer Architecture. IEEE, New York, (1985) 276-283.

Digital Library

[9]

Papamarcos, M. and Patel, J. A low overhead coherence solution for multiprocessors with private cache memories. In Proc. of the l lth Int. Syrup. on Computer Architecture. IEEE, New York, (1984) 348-354.

Digital Library

[10]

Goodman, J.R. Using cache memory to reduce Processor-memory traffic. In Proc. of the 1Oth Int. Syrup. on Computer Architecture. IEEE, New York, (1983) 124-131.

Digital Library

[11]

Thacket, C.P., Stewart, L.C. and Satterthwaite, E.H. Firefly: a multiprocessor workstation. IEEE Trans. Computers, C-37, 8 (1988), 909-920.

Digital Library

[12]

Monler, L. and Sindhu, P. The architecture of the dragon. In Proc. of the Thirtieth IEEE Int. Conf. (1985), 118-121.

[13]

Hoogendoorn, C.H. Reduction of memory interference in multiprocessor systems. In Proc. 4th Annual Syrup. Computer Architecture, IEEE, New York, (1977) 179-183.

Digital Library

[14]

Tang, C.K. Cache system design in the tightly coupled multilm3cessor system. In Proc. of AFIPS National Computer Conference. 45 (1976), 749- 753.

[15]

Censier, L.M. and Feaulrier, P. A new solution to coherence problems in multicache systems. IEEE Trans. Computers 27, 12 (1978), 1112-1118.

[16]

Dubois, M. and Briggs, F. Effects of cache coherency in multiprocessors. IEEE Trans. Computers 31, 11 (1982), 1083-1099.

[17]

Yen, W.C. and Fu, K.S. Coherence problem in a multicache system. In Proc. of the Int. Conf. on Parallel Processing. 1EEE, New Yock, 1982, 332- 339.

[18]

Archibald, J. and Baer, J-L. An economical solution to the cache coherence problem. In Proc. of the 11th Int. Syrup. on Computer Architecture, IEEE New York, (1984), 355-362.

Digital Library

[19]

Archibald, J., and Baer, J-L. Cache coherence protocols: Evaluation using a multiprocessor simulation model. ACM Trans. on Computer Systems 4, 4 (1986), 273-298.

Digital Library

[20]

Sweazey, P. and Smith, A.J. A class of compatible cache consistency protocols and their support by the IEEE. Futurebus. In Proc. of the 13th Int. Syrup. on Computer Architecture, I~.R~ New York, (1986) 414-423.

Digital Library

[21]

Prete, C.A. The RST cache memory design for a tightly coupled multiprocessor system. IEEE Micro, 11, 2, 16-19 40-52.

Digital Library

[22]

Thacker C.P. and Stewart L.C. Firefly: a Multiprocessor Workstation. 1987 ACM 0-89791- 238-1/87.

[23]

D.M. Ritchie and K. Thompson The UNIX timesharing system. Commun. ACM 17, 7 (July 1974), 365-375.

Digital Library

[24]

J. S. Quaterman, A. Silberschatz and J.L. Petetson 4.2BSD and 4.3BSD as examples of the UNIX system. ACM Computing Surveys 17, 4 (Dec. 1985), 379-418.

Digital Library

[25]

M.J. Bach and SJ. Buroff Multiprocessor UNIX operating systems. AT&T Bell Laboratories Technical Journal 63, 8 (Oct. 1984), 1733-1749.

[26]

Prete, C.A., Lazzerini, B., and Corsini, P. A kernel for a multiprocessor system with anonymous processes. In Proc. of the Int. Conf. on Parallel Processing and Applications eds. E. Chidcozzi and A. D'Amico. North-Holland (Sept. 1987), 71-78.

Cited By

Prete CRicciardi LPrina G(1995)Reducing coherence-related overhead in multiprocessor systemsProceedings Euromicro Workshop on Parallel and Distributed Processing10.1109/EMPDP.1995.389177(444-451)Online publication date: 1995
https://doi.org/10.1109/EMPDP.1995.389177
Prete CPrina GRicciardi L(1995)A Trace-Driven Simulator for Performance Evaluation of Cache-Based Multiprocessor SystemsIEEE Transactions on Parallel and Distributed Systems10.1109/71.4666306:9(915-929)Online publication date: 1-Sep-1995
https://dl.acm.org/doi/10.1109/71.466630
Prete C(1994)Cachesim: A graphical software environment to support the teaching of computer systems with Cache memoriesSoftware Engineering Education10.1007/BFb0017623(317-327)Online publication date: 1994
https://doi.org/10.1007/BFb0017623

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Published In

cover image ACM Conferences

ACMSE '92: Proceedings of the 30th annual ACM Southeast Regional Conference

April 1992

487 pages

ISBN:0897915062

DOI:10.1145/503720

General Chair:
Mladen A. Vouk
North Carolina State University, Raleigh, NC
,
Program Chairs:
Douglas S. Reeves
North Carolina State University, Raleigh, NC
,
Cherri M. Pancake
Auburn University, AL

Copyright © 1992 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 08 April 1992

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April 8 - 10, 1992

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Cited By

Prete CRicciardi LPrina G(1995)Reducing coherence-related overhead in multiprocessor systemsProceedings Euromicro Workshop on Parallel and Distributed Processing10.1109/EMPDP.1995.389177(444-451)Online publication date: 1995
https://doi.org/10.1109/EMPDP.1995.389177
Prete CPrina GRicciardi L(1995)A Trace-Driven Simulator for Performance Evaluation of Cache-Based Multiprocessor SystemsIEEE Transactions on Parallel and Distributed Systems10.1109/71.4666306:9(915-929)Online publication date: 1-Sep-1995
https://dl.acm.org/doi/10.1109/71.466630
Prete C(1994)Cachesim: A graphical software environment to support the teaching of computer systems with Cache memoriesSoftware Engineering Education10.1007/BFb0017623(317-327)Online publication date: 1994
https://doi.org/10.1007/BFb0017623

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