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The ultimate RISC

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Douglas W. JonesAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 16, Issue 3

Pages 48 - 55

https://doi.org/10.1145/48675.48683

Published: 01 June 1988 Publication History

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Abstract

Reduced instruction set computer (RISC) architectures have attracted considerable interest during the past decade. The ultimate RISC architecture presented here is an extreme yet simple illustration of such an architecture. It has only one instruction, move memory to memory, yet it is useful.

References

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[2] Hennessy, J. et al. Hardware/Software Tradeoffs for Increased Performance. Proc. Symp. on Architectural Support for Programming Languages and Operating Systems, Mar. 1982, Palo Alto, California, 2-11; published as Computer Architecture News, 10, 2 (Mar. 1982).

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[3] Introduction to the IAPX 432 Architecture. Intel Corporation, Santa Clara, Calif. 1981.

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[4] Johnsson, R. K., and Wick, J. D. An Overview of the Mesa Processor Architecture. Proc. Symp. on Architectural Support for Programming Languages and Operating Systems, Mar. 1982, Palo Alto, California, 20-29; published as Computer Architecture News, 10, 2 (Mar. 1982).

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[5] Jones, D. W. Systematic Protection Mechanism Design. Proc. Symp. on Architectural Support for Programming Languages and Operating Systems, Mar. 1982, Palo Alto, California, 77-80; published as Computer Architecture News, 10, 2 (Mar. 1982).

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[6] Jones, D. W. Assembly Language as Object Code. Software - Practice and Experience, 13, 8 (Aug. 1983) 715-725.

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[7] Jones, D. W. Machine Independent SMAL: A Symbolic Macro Assembly Language. Technical Report 84-09, Department of Computer Science, University of Iowa, Iowa City, 1984.

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[8] Patterson, D. A. Reduced Instruction Set Computers. Communications of the ACM, 28, 1 (Jan. 1985) 8-21.

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Kissner MBino LPäsler FCaruana PGhalanos G(2024)An All-Optical General-Purpose CPU and Optical Computer ArchitectureJournal of Lightwave Technology10.1109/JLT.2024.345845942:22(7999-8013)Online publication date: 15-Nov-2024
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Index Terms

The ultimate RISC
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Very long instruction word
    2. Serial architectures

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cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 16, Issue 3

June 1988

81 pages

ISSN:0163-5964

DOI:10.1145/48675

Editor:
Doug DeGroot

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 June 1988

Published in SIGARCH Volume 16, Issue 3

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https://doi.org/10.1109/JLT.2024.3458459
Ismail KGhany M(2021)Survey on Machine Learning Algorithms Enhancing the Functional Verification ProcessElectronics10.3390/electronics1021268810:21(2688)Online publication date: 3-Nov-2021
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Sakamoto NAhmed TAnderson JHara-Azumi Y(2017)Subleq $_\circleddash$ : An Area-Efficient Two-Instruction-Set ComputerIEEE Embedded Systems Letters10.1109/LES.2017.26664809:2(33-36)Online publication date: 1-Jun-2017
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Sima MVassiliadis SCotofana S(2007)A Taxonomy of Field-Programmable Custom Computing MachinesFine- and Coarse-Grain Reconfigurable Computing10.1007/978-1-4020-6505-7_7(299-378)Online publication date: 2007
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RISC Microprocessors, History and Overview

A microcoded RISC

The HP PA-8000 RISC CPU

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