article

Automated design of finite state machine predictors for customized processors

Authors:

Timothy Sherwood,

Brad CalderAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 29, Issue 2

Pages 86 - 97

https://doi.org/10.1145/384285.379254

Published: 01 May 2001 Publication History

Abstract

Customized processors use compiler analysis and design automation techniques to take a generalized architectural model and create a specific instance of it which is optimized to a given application or set of applications. These processors offer the promise of satisfying the high performance needs of the embedded community while simultaneously shrinking design times.

Finite State Machines (FSM) are a fundamental building block in computer architecture, and are used to control and optimize all types of prediction and speculation, now even in the embedded space. They are used for branch prediction, cache replacement policies, and confidence estimation and accuracy counters for a variety of optimizations.

In this paper, we present a framework for automated design of small FSM predictors for customized processors. Our approach can be used to automatically generate small FSM predictors to perform well over a suite of applications, tailored to a specific application, or even a specific instruction. We evaluate the use of these customized FSM predictors for branch prediction over a set of benchmarks.

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Cited By

Zhou CHuang LLi ZZhang TDou QBehjat LHan JVelev MChen D(2017)Design Space Exploration of TAGE Branch Predictor with Ultra-Small RAMProceedings of the on Great Lakes Symposium on VLSI 201710.1145/3060403.3060423(281-286)Online publication date: 10-May-2017
https://dl.acm.org/doi/10.1145/3060403.3060423
Emma P(2010)Branch PredictionSpeculative Execution in High Performance Computer Architectures10.1201/9781420035155.ch3(29-85)Online publication date: 14-Jan-2010
https://doi.org/10.1201/9781420035155.ch3
Petrov POrailoglu A(2005)A reprogrammable customization framework for efficient branch resolution in embedded processorsACM Transactions on Embedded Computing Systems10.1145/1067915.10679244:2(452-468)Online publication date: May-2005
https://doi.org/10.1145/1067915.1067924
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Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 29, Issue 2

Special Issue: Proceedings of the 28th annual international symposium on Computer architecture (ISCA '01)

May 2001

262 pages

ISSN:0163-5964

DOI:10.1145/384285

Editor:
Per Stenström
Chalmers Univ. of Technology

Issue’s Table of Contents

ISCA '01: Proceedings of the 28th annual international symposium on Computer architecture
June 2001
289 pages
ISBN:0769511627
DOI:10.1145/379240
Chairman:
Per Stenström
Chalmers Univ. of Technology

Copyright © 2001 Authors.

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 May 2001

Published in SIGARCH Volume 29, Issue 2

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Cited By

Zhou CHuang LLi ZZhang TDou QBehjat LHan JVelev MChen D(2017)Design Space Exploration of TAGE Branch Predictor with Ultra-Small RAMProceedings of the on Great Lakes Symposium on VLSI 201710.1145/3060403.3060423(281-286)Online publication date: 10-May-2017
https://dl.acm.org/doi/10.1145/3060403.3060423
Emma P(2010)Branch PredictionSpeculative Execution in High Performance Computer Architectures10.1201/9781420035155.ch3(29-85)Online publication date: 14-Jan-2010
https://doi.org/10.1201/9781420035155.ch3
Petrov POrailoglu A(2005)A reprogrammable customization framework for efficient branch resolution in embedded processorsACM Transactions on Embedded Computing Systems10.1145/1067915.10679244:2(452-468)Online publication date: May-2005
https://doi.org/10.1145/1067915.1067924
Khan TUgur MNathella KSunwoo DLitz HJimenez DKasikci B(2022)Whisper: Profile-Guided Branch Misprediction Elimination for Data Center Applications2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO56248.2022.00017(19-34)Online publication date: Oct-2022
https://doi.org/10.1109/MICRO56248.2022.00017
Zhao LHou RWang KSu YLi PMeng D(2021)A Novel Probabilistic Saturating Counter Design for Secure Branch PredictorJournal of Computer Science and Technology10.1007/s11390-021-1253-836:5(1022-1036)Online publication date: 30-Sep-2021
https://doi.org/10.1007/s11390-021-1253-8
Cummings PCrooks A(2020)Development of a Hybrid Machine Learning Agent Based Model for Optimization and InterpretabilitySocial, Cultural, and Behavioral Modeling10.1007/978-3-030-61255-9_15(151-160)Online publication date: 11-Oct-2020
https://doi.org/10.1007/978-3-030-61255-9_15
Zhou CHuang LLi ZZhang TDou QBehjat LHan JVelev MChen D(2017)Design Space Exploration of TAGE Branch Predictor with Ultra-Small RAMProceedings of the Great Lakes Symposium on VLSI 201710.1145/3060403.3060423(281-286)Online publication date: 10-May-2017
https://dl.acm.org/doi/10.1145/3060403.3060423
(2015)2-Bit Branch Predictor Modeling Using Markov ModelProcedia Computer Science10.1016/j.procs.2015.08.51762(467-469)Online publication date: 2015
https://doi.org/10.1016/j.procs.2015.08.517
Sherwood TOskin MCalder BIrwin MZhao WLavagno LMahlke S(2004)Balancing design options with SherpaProceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems10.1145/1023833.1023843(57-68)Online publication date: 22-Sep-2004
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