Article

Efficient schemes to scale the interconnection network bandwidth in a ring-based multiprocessor system

Authors:

Byoung Soon Jang,

Sung Woo Chung,

Seong Tae Jhang,

Chu Shik JhonAuthors Info & Claims

SAC '01: Proceedings of the 2001 ACM symposium on Applied computing

Pages 510 - 516

https://doi.org/10.1145/372202.372447

Published: 01 March 2001 Publication History

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References

[1]

K. Hwang and Z. Xu, Scalable Parallel Computing: Technology, Architecture, Programming, McGrawHill, 1998.

Digital Library

Google Scholar

[2]

IEEE Computer Society, IEEE Standard for Scalable Coherent Interface(SCI), Institute of Electrical and Electronics Engineers, August 1993.

Google Scholar

[3]

Tom Lovett and Russell Clapp, "STING : A CC-NUMA Computer System for the Commercial Marketplace", In Proc. of the 23th International Symposium on Computer Architecture(ISCA), pp. 308-317, May 1996.

Digital Library

Google Scholar

[4]

Z. Vranesic, et al., "The NUMAchine Multiprocessor", Department of Computer Science, Toronto Univ., 1995.

Google Scholar

[5]

Barroso, L.A., and Dubois, M., "Cache coherence on a slotted ring", Proc. 1991 Int'l Conf. Parallel Processing, vol. 1, pp. 1230-1237, St. Charles, III., Aug. 1991.

Google Scholar

[6]

Barroso, L.A., and Dubois, M., "Performance Evaluation of the Slotted-Ring Multiprocessor", IEEE Transactions on Computers, Vol. 44, No. 7, pp.878-890, July 1995.

Digital Library

Google Scholar

[7]

Sung Woo Chung, Seong Tae Jhang and Chu Shik Jhon, "PANDA : Ring-Based Multiprocessor System using New Snooping Protocol", In Proc. of the 1998 International Conference on Parallel and Distributed Systems(ICPADS), pp. 10-17, Dec. 1998.

Digital Library

Google Scholar

[8]

"Focus: Growing the Standard Base for High Volume Server", Available in http://developer.intel.com/update/archive/issue5/focus.htm

Google Scholar

[9]

"8-way and 4-way IntelR PentiumR III XeonTM Processorbased Servers", Avaiable in http://www.intel.com/eBusiness/server/resources/pentiumiii/ xeon/8way/overview.htm

Google Scholar

[10]

Daniel Lenoski, et al., "The Stanford Dash Multiprocessor", IEEE Computer, March 1992.

Digital Library

Google Scholar

[11]

Zhang, Z. and J. Torrellas, "Reducing Remote Conflict Misses: NUMA with Remote Cache versus COMA", In Proc. of the 3rd IEEE Symp. on High Performance Computer Architecture(HPCA), pp. 272-281, Feb. 1997.

Digital Library

Google Scholar

[12]

R. H. Katz, et al., "Implementing a Cache Consistency Protocol", In Proc. of the 12th International Symposium on Computer Architecture(ISCA), pp. 276-283, June 1985.

Digital Library

Google Scholar

[13]

SES/Workbench Technical Reference, Scientific and Engineering Software, 1995.

Google Scholar

[14]

"Transaction Processing Performance Council, Overview of the TPC Benchmark A:", Available in http://www.tpc.org/adetail.html

Google Scholar

[15]

"AViiON AV 25000 ccNUMA Server", Available in http ://www.dg.com/aviion/html/av_25000_enterprise_s erver.html

Google Scholar

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Kwak JJhon C(2018)Torus RingParallel Computing10.1016/j.parco.2006.10.00133:1(2-20)Online publication date: 31-Dec-2018
https://dl.acm.org/doi/10.1016/j.parco.2006.10.001
Suh HChung SBartolini SFoglia PGiorgi RPrete C(2004)DRACOProceedings of the 2004 workshop on MEmory performance: DEaling with Applications , systems and architecture10.1145/1152922.1101872(10-16)Online publication date: 29-Sep-2004
https://dl.acm.org/doi/10.1145/1152922.1101872
Suh HChung S(2004)DRACOACM SIGARCH Computer Architecture News10.1145/1101868.110187233:3(10-16)Online publication date: 29-Sep-2004
https://dl.acm.org/doi/10.1145/1101868.1101872
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SAC '01: Proceedings of the 2001 ACM symposium on Applied computing

March 2001

692 pages

ISBN:1581132875

DOI:10.1145/372202

Chairman:
G. B. Lamont
Air Force Institute of Technology

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 March 2001

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Kwak JJhon C(2018)Torus RingParallel Computing10.1016/j.parco.2006.10.00133:1(2-20)Online publication date: 31-Dec-2018
https://dl.acm.org/doi/10.1016/j.parco.2006.10.001
Suh HChung SBartolini SFoglia PGiorgi RPrete C(2004)DRACOProceedings of the 2004 workshop on MEmory performance: DEaling with Applications , systems and architecture10.1145/1152922.1101872(10-16)Online publication date: 29-Sep-2004
https://dl.acm.org/doi/10.1145/1152922.1101872
Suh HChung S(2004)DRACOACM SIGARCH Computer Architecture News10.1145/1101868.110187233:3(10-16)Online publication date: 29-Sep-2004
https://dl.acm.org/doi/10.1145/1101868.1101872
Joo Beom Yun Seong Tae Jhang Chu Shik Jhon Cheol Won Lee (2002)Analysis of system performance by changing the ring architecture on the dual ring CC-NUMA systemNinth International Conference on Parallel and Distributed Systems, 2002. Proceedings.10.1109/ICPADS.2002.1183385(103-108)Online publication date: 2002
https://doi.org/10.1109/ICPADS.2002.1183385

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A multilayer nanophotonic interconnection network for on-chip many-core communications

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Silicon-photonic network architectures for scalable, power-efficient multi-chip systems

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