FazyRV: Closing the Gap between 32-Bit and Bit-Serial RISC-V Cores with a Scalable Implementation
Pages 240 - 248
Abstract
RISC-V processor cores with a 32-bit internal data path reach a boundary on their minimal size, requiring novel concepts to decrease silicon area and the cost of Internet of Things (IoT) devices. We propose a minimal-area open-source RV32I RISC-V core targeting the IoT and low-workload applications. Unlike cores with a similarly small area, FazyRV is inherently scalable to a data path width of 1, 2, 4, or 8 bits. FazyRV has manifold variants to achieve the smallest footprint at given performance requirements. This paper provides insight into FazyRV, its verification, and the resource utilization for five Field-Programmable Gate Array (FPGA) architectures. We also compare its performance with similar cores using the Embench benchmark suite. Based on the findings, we analyze and discuss optimization potentials in depth. Although FazyRV is implemented at the register transfer level, we achieve comparable results to hand-optimized cores at the gate level. In an exemplary IoT application, the whole system on chip is implemented in 77 Slices, or 645 Logic Cells for a Xilinx/AMD 7-Series or an iCE40 FPGA, respectively.
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Index Terms
- FazyRV: Closing the Gap between 32-Bit and Bit-Serial RISC-V Cores with a Scalable Implementation
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May 2024
345 pages
ISBN:9798400705977
DOI:10.1145/3649153
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Published: 02 July 2024
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