Article

Free access

Compiler controlled value prediction using branch predictor based confidence

Authors:

Eric Larson,

Todd AustinAuthors Info & Claims

MICRO 33: Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture

Pages 327 - 336

https://doi.org/10.1145/360128.360164

Published: 01 December 2000 Publication History

PDF eReader Publisher Site

Supplementary Material

PS File (p327-larson.ps)

Download
830.77 KB

References

[1]

D.C. Burger and T. M. Austin, "The SimpleScalar Tool Set, Version 2.00, University of Wisconsin Computer Sciences Technical Report #1342, June 1997.

Google Scholar

[2]

B. Calder, P. Feller, and A. Eustace, Value Profiling and Optimization, in Journal of Instruction-Level Parallelism, March 1999.

Google Scholar

[3]

B. Calder, G. Reinman, and D. M. Tullsen, Selective Value Prediction, in 26th International Symposium of Computer Architecture, May 1999.

Digital Library

Google Scholar

[4]

C. Fu. and T. M. Conte, Value Speculation Mechanisms for EPIC Architectures, Technical Report. Dept. of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC 27695-7911, October 1998.

Google Scholar

[5]

C. Fu, M. D. Jennings, S. Y. Larin, and T. M. Conte, Software-Only Value Speculation Scheduling, Techni - calReport. Dept. of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC 27695-7911, June 1998

Google Scholar

[6]

C. Fu, M. D. Jennings, S. Y. Larin, and T. M. Conte, Value Speculation Scheduling for High Performance Processors, in 8th International Conference on Architectural Support for Programming Languages and Operating Systems, October 1998.

Digital Library

Google Scholar

[7]

D. Grunwald, A. Klauser, S. Manne, and A. Pleskun, Confidence Estimation for Speculation Control, in 25th International Symposium of Computer Architecture, June 1998.

Digital Library

Google Scholar

[8]

J. Huang, Y. Choi, D. J. Lilja, Improving Value Prediction by Exploiting Both Operand and Output Value Locality, Laboratory for Advanced Research in Computing Technology and Compilers Technical Report No. ARCTiC 99-06, July 1999.

Google Scholar

[9]

K. M. Lepak and M. H. Lipasti, On the Value Locality of Store Instructions, in 27th International Symposium of Computer Architecture, June 2000.

Digital Library

Google Scholar

[10]

M. H. Lipasti and J. P. Shen, Exploiting Value Locality to Exceed the Dataflow Limit, in 29th International Symposium on Microarchitecture, December 1996.

Digital Library

Google Scholar

[11]

M. H. Lipasti and J. P. Shen, The Performance Potential of Value and Dependence Prediction, in EUROPAR-97, August 1997.

Digital Library

Google Scholar

[12]

S. Lee, Y. Wang, P.Yew, "Decoupled Value Prediction on Trace Processors, in 6th International Symposium on High Performance Computer Architecture, January 2000.

Google Scholar

[13]

P. Marcuello and A. Gonzalez, The Potential of Data Value Speculation to Boost ILP, in 12th International Conference on Supercomputing, July 1998.

Digital Library

Google Scholar

[14]

P. Marcuello and A. Gonzalez, A Quantitative Assessment of Thread-Level Speculation Techniques, in 1st International Parallel and Distributed Processing Symposium, May 2000.

Digital Library

Google Scholar

[15]

P. Marcuello, J. Tubella, and A. Gonzalez, Value Prediction for Speculative Multithreaded Architectures in 32th International Symposium on Microarchitecture, November 1999.

Digital Library

Google Scholar

[16]

R. Muth, S. Debray, S. Watterson, and K. De Bosschere, alto: A Link-Time Optimizer for the Compaq Alpha, University of Arizona Computer Sciences Technical Report 98-14, December 1998.

Google Scholar

[17]

T. Nakra, R. Gupta, and M. L. Soffa, Global Context- Based Value Prediction, in 5th International Symposium on High Performance Computer Architecture, January 1999.

Digital Library

Google Scholar

[18]

T. Nakra, R. Gupta, and M. L. Soffa, Value Prediction in VLIW Machines, in 26th International Symposium on Computer Architecture, May 1999.

Digital Library

Google Scholar

[19]

Y. Sazeides and J. E. Smith, The Predictability of Data Values, in 30th International Symposium on Microarchitecture, December 1997.

Digital Library

Google Scholar

[20]

A. Sodani and G. Sohi, Dynamic Instruction Reuse, in 24th International Symposium on Computer Architecture, June 1997.

Digital Library

Google Scholar

[21]

E. Schnarr and J. Larus, Fast Out-Of-Order Processor Simulation Using Memoization, in 8th International Conference on Architectural Support for Programming Languages and Operating Systems, October 1998.

Digital Library

Google Scholar

[22]

S. T. Srinivasan and A. R. Lebeck, Load Latency Tolerance in Dynamically Scheduled Processors, in 31st International Symposium on Microarchitecture, December 1998.

Digital Library

Google Scholar

[23]

D. M. Tullsen, J. S. Seng, Storageless Value Prediction Using Prior Register Values, in 26th International Symposium on Computer Architecture, May 1999.

Digital Library

Google Scholar

[24]

VTune TM Performance Analyzer Home Page, http:// developer.intel.com/vtune/analyzer/index.htm

Google Scholar

[25]

C. B. Zilles and G. Sohi, Understanding the Backwards Slices of Performance Degrading Instructions, in 27th International Symposium of Computer Architecture, June 2000.

Digital Library

Google Scholar

Cited By

View all

Mittal S(2017)A survey of value prediction techniques for leveraging value localityConcurrency and Computation: Practice and Experience10.1002/cpe.425029:21Online publication date: 11-Sep-2017
https://doi.org/10.1002/cpe.4250
Puiggali JSzymanski BJové TMarzo J(2012)Dynamic branch speculation in a speculative parallelization architecture for computer clustersConcurrency and Computation: Practice and Experience10.1002/cpe.287225:7(932-960)Online publication date: 29-Jun-2012
https://doi.org/10.1002/cpe.2872
Smith JGonzalez AMarcuello PSazeides Y(2010)Data SpeculationSpeculative Execution in High Performance Computer Architectures10.1201/9781420035155.ch9(215-243)Online publication date: 14-Jan-2010
https://doi.org/10.1201/9781420035155.ch9
Show More Cited By

Recommendations

NTB branch predictor: dynamic branch predictor for high-performance embedded processors

Branch prediction accuracy becomes more crucial in high-performance embedded processors. The importance of branch prediction in embedded processors continues to grow in the future. Many branch predictors have been proposed to alleviate the performance ...
A novel meta predictor design for hybrid branch prediction

Recent systems have been paved the way for being high-performance due to the super-pipelining, dynamic scheduling and superscalar processor technologies. The performance of the system is greatly affected by the accuracy of the branch prediction because ...
Classification-directed branch predictor design

Comments

Information & Contributors

Information

Published In

MICRO 33: Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture

December 2000

357 pages

ISBN:1581131968

DOI:10.1145/360128

Chairmen:
Andrew Wolfe
S3 Incorporated
,
Michael Schlansker
Hewlett-Packard

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 December 2000

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

MICRO00

Sponsor:

IEEE TC - MICRO
SIGMICRO

MICRO00: 33rd Annual International Symposium on Microarchitecture

California, Monterey, USA

Acceptance Rates

MICRO 33 Paper Acceptance Rate 31 of 110 submissions, 28%;

Overall Acceptance Rate 484 of 2,242 submissions, 22%

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

11
Total Citations
View Citations
505
Total Downloads

Downloads (Last 12 months)75
Downloads (Last 6 weeks)16

Reflects downloads up to 13 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

View all

Mittal S(2017)A survey of value prediction techniques for leveraging value localityConcurrency and Computation: Practice and Experience10.1002/cpe.425029:21Online publication date: 11-Sep-2017
https://doi.org/10.1002/cpe.4250
Puiggali JSzymanski BJové TMarzo J(2012)Dynamic branch speculation in a speculative parallelization architecture for computer clustersConcurrency and Computation: Practice and Experience10.1002/cpe.287225:7(932-960)Online publication date: 29-Jun-2012
https://doi.org/10.1002/cpe.2872
Smith JGonzalez AMarcuello PSazeides Y(2010)Data SpeculationSpeculative Execution in High Performance Computer Architectures10.1201/9781420035155.ch9(215-243)Online publication date: 14-Jan-2010
https://doi.org/10.1201/9781420035155.ch9
Trias APuiggalí JCastro FJové TSbert MMarzo J(2009)Speculative parallelization of multipath radiosity algorithmProceedings of the 12th international conference on Symposium on Performance Evaluation of Computer & Telecommunication Systems10.5555/1688291.1688305(89-95)Online publication date: 13-Jul-2009
https://dl.acm.org/doi/10.5555/1688291.1688305
Li XYang CDu ZNgai T(2005)Exploiting thread-level speculative parallelism with software value predictionProceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture10.1007/11572961_29(367-388)Online publication date: 24-Oct-2005
https://dl.acm.org/doi/10.1007/11572961_29
Zhao QLilja D(2004)Static classification of value predictability using compiler hintsIEEE Transactions on Computers10.1109/TC.2004.4953:8(929-944)Online publication date: 1-Aug-2004
https://dl.acm.org/doi/10.1109/TC.2004.49
Zhou HFlanagan JConte T(2003)Detecting global stride locality in value streamsACM SIGARCH Computer Architecture News10.1145/871656.85965631:2(324-335)Online publication date: 1-May-2003
https://dl.acm.org/doi/10.1145/871656.859656
Zhou HFlanagan JConte TGottlieb ALi K(2003)Detecting global stride locality in value streamsProceedings of the 30th annual international symposium on Computer architecture10.1145/859618.859656(324-335)Online publication date: 9-Jun-2003
https://dl.acm.org/doi/10.1145/859618.859656
Fu CBodine JConte T(2003)Modeling Value SpeculationIEEE Transactions on Computers10.1109/TC.2003.118394452:3(277-292)Online publication date: 1-Mar-2003
https://dl.acm.org/doi/10.1109/TC.2003.1183944
Sazeides Y(2002)Modeling value speculationProceedings Eighth International Symposium on High Performance Computer Architecture10.1109/HPCA.2002.995711(211-222)Online publication date: 2002
https://doi.org/10.1109/HPCA.2002.995711
Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

NTB branch predictor: dynamic branch predictor for high-performance embedded processors

A novel meta predictor design for hybrid branch prediction

Classification-directed branch predictor design

Comments

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Qualifiers

Conference

Acceptance Rates

Other Metrics

Article Metrics

Other Metrics

Cited By

PDF

eReader

Login options

Full Access

Supplementary Material

References

Cited By

Index Terms

Recommendations

NTB branch predictor: dynamic branch predictor for high-performance embedded processors

A novel meta predictor design for hybrid branch prediction

Classification-directed branch predictor design

Comments

Information

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Qualifiers

Conference

Acceptance Rates

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

View options

PDF

eReader

Login options

Full Access

Figures

Other

Share

Share this Publication link

Share on social media

Affiliations