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Technology/Memory Co-Design and Co-Optimization Using E-Tree Interconnect

Authors:

Mahta Mayahinia,

Hsiao-Hsuan Liu,

Francky Catthoor,

Chenyun PanAuthors Info & Claims

GLSVLSI '23: Proceedings of the Great Lakes Symposium on VLSI 2023

Pages 159 - 162

https://doi.org/10.1145/3583781.3590311

Published: 05 June 2023 Publication History

Abstract

For on-chip SRAM, a major portion of delay and energy is contributed by the H-Tree interconnects. In this paper, we propose an E-Tree interconnect technology to minimize the H-Tree delay and energy overheads based on an efficient interconnect technology/memory co-design framework for nonuniform workloads. Various array- and interconnect-level design parameters are co-designed for optimal performance using three emerging interconnect materials with a realistic cell library.

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Digital Library

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Cited By

Pei ZLiu HMayahinia MTahoori MCatthoor FTőkei ZAbdi DMyers JPan C(2024)Ultra-Scaled E-Tree-Based SRAM Design and Optimization With Interconnect FocusIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2024.343816471:10(4597-4610)Online publication date: Oct-2024
https://doi.org/10.1109/TCSI.2024.3438164
Mayahinia MMarinelli TPei ZLiu HPan CTokei ZCatthoor FTahoori M(2024)Dynamic Segmented Bus for Energy-Efficient Last-Level Cache in Advanced Interconnect-Dominant NodesIEEE Embedded Systems Letters10.1109/LES.2024.344471116:4(321-324)Online publication date: Dec-2024
https://doi.org/10.1109/LES.2024.3444711
Liu HCatthoor FLiu HCatthoor F(2024)Macro-level Performance-Power-Area Benchmark of CFET SRAM MacroCircuit-Technology Co-Optimization of SRAM Design in Advanced CMOS Nodes10.1007/978-3-031-76109-6_7(173-187)Online publication date: 21-Dec-2024
https://doi.org/10.1007/978-3-031-76109-6_7
Show More Cited By

Index Terms

Technology/Memory Co-Design and Co-Optimization Using E-Tree Interconnect
1. Hardware
  1. Integrated circuits
    1. Interconnect
    2. Semiconductor memory
      1. Static memory

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Published In

cover image ACM Conferences

GLSVLSI '23: Proceedings of the Great Lakes Symposium on VLSI 2023

June 2023

731 pages

ISBN:9798400701252

DOI:10.1145/3583781

General Chairs:
Himanshu Thapliyal
University of Tennessee, Knoxville, USA
,
Ronald DeMara
University of Central Florida, USA
,
Program Chairs:
Inna Partin-Vaisband
University of Illinois Chicago, USA
,
Srinivas Katkoori
University of South Florida, USA

Copyright © 2023 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Publication History

Published: 05 June 2023

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GLSVLSI '23

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SIGDA

GLSVLSI '23: Great Lakes Symposium on VLSI 2023

June 5 - 7, 2023

TN, Knoxville, USA

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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June 30 - July 2, 2025

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Cited By

Pei ZLiu HMayahinia MTahoori MCatthoor FTőkei ZAbdi DMyers JPan C(2024)Ultra-Scaled E-Tree-Based SRAM Design and Optimization With Interconnect FocusIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2024.343816471:10(4597-4610)Online publication date: Oct-2024
https://doi.org/10.1109/TCSI.2024.3438164
Mayahinia MMarinelli TPei ZLiu HPan CTokei ZCatthoor FTahoori M(2024)Dynamic Segmented Bus for Energy-Efficient Last-Level Cache in Advanced Interconnect-Dominant NodesIEEE Embedded Systems Letters10.1109/LES.2024.344471116:4(321-324)Online publication date: Dec-2024
https://doi.org/10.1109/LES.2024.3444711
Liu HCatthoor FLiu HCatthoor F(2024)Macro-level Performance-Power-Area Benchmark of CFET SRAM MacroCircuit-Technology Co-Optimization of SRAM Design in Advanced CMOS Nodes10.1007/978-3-031-76109-6_7(173-187)Online publication date: 21-Dec-2024
https://doi.org/10.1007/978-3-031-76109-6_7
Liu HCatthoor FLiu HCatthoor F(2024)SRAM Operations and Simulation Methodologies at Bitcell, Subarray, and Macro LevelsCircuit-Technology Co-Optimization of SRAM Design in Advanced CMOS Nodes10.1007/978-3-031-76109-6_2(23-55)Online publication date: 23-Oct-2024
https://doi.org/10.1007/978-3-031-76109-6_2
Liu HCatthoor FLiu HCatthoor F(2024)Conclusions, Contributions, and Future WorksCircuit-Technology Co-Optimization of SRAM Design in Advanced CMOS Nodes10.1007/978-3-031-76109-6_10(249-260)Online publication date: 21-Dec-2024
https://doi.org/10.1007/978-3-031-76109-6_10
Liu HCatthoor FLiu HCatthoor F(2024)IntroductionCircuit-Technology Co-Optimization of SRAM Design in Advanced CMOS Nodes10.1007/978-3-031-76109-6_1(1-20)Online publication date: 21-Dec-2024
https://doi.org/10.1007/978-3-031-76109-6_1
Liu HSchuddinck PPei ZVerschueren LMertens HSalahuddin SHiblot GXiang YChan BSubramanian SWeckx PHellings GBardon MRyckaert JPan CCatthoor F(2023)CFET SRAM With Double-Sided Interconnect Design and DTCO BenchmarkIEEE Transactions on Electron Devices10.1109/TED.2023.330532270:10(5099-5106)Online publication date: Oct-2023
https://doi.org/10.1109/TED.2023.3305322

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