research-article

SiFI-AI: A Fast and Flexible RTL Fault Simulation Framework Tailored for AI Models and Accelerators

Authors:

Jürgen BeckerAuthors Info & Claims

GLSVLSI '23: Proceedings of the Great Lakes Symposium on VLSI 2023

Pages 287 - 292

https://doi.org/10.1145/3583781.3590226

Published: 05 June 2023 Publication History

Abstract

For AI-based systems in safety-critical domains, it is inevitable to understand the impact of random hardware faults affecting the target hardware accelerators. The high degree of data reuse makes Deep Neural Network (DNN) accelerators susceptible to significant fault propagation and hence hazardous predictions. Therefore, we present SiFI-AI, a simulation framework for fault injection in DNN accelerators. SiFI-AI proposes a hybrid simulation approach combining fast AI inference with cycle-accurate RTL simulation. Time-expensive RTL simulation is only used to accurately target registers in the hardware through condition-based fault injection. This enables to reveal vulnerable DNN layers and the related fault origin. In a resilience study with 1.5~M fault injection experiments, we analyze representative DNNs and a state-of-the-art DNN accelerator to identify vulnerable layers. The study only takes 1.15 days which is 7x faster than state-of-the-art. Our experiments show the high impact of control register faults and that narrow and deep layers are 10x more resilient compared to the wide and shallow layers of a DNN.

References

[1]

Alon Amid, et al. 2020. Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs. IEEE Micro, Vol. 40, 4 (2020), 10--21.

Digital Library

[2]

Josie E. Rodriguez Condia, Fernando Fernandes dos Santos, Matteo Sonza Reorda, and Paolo Rech. 2021. Combining Architectural Simulation and Software Fault Injection for a Fast and Accurate CNNs Reliability Evaluation on GPUs. In 2021 IEEE 39th VLSI Test Symposium (VTS). 1--7.

[3]

Jia Deng, et al. 2009. ImageNet: A large-scale hierarchical image database. In 2009 IEEE Conference on Computer Vision and Pattern Recognition. 248--255.

[4]

Nael Fasfous, et al. 2021. Binary-LoRAX: Low-Latency Runtime Adaptable XNOR Classifier for Semi-Autonomous Grasping with Prosthetic Hands., 13430--13437 pages.

[5]

Hasan Genc, et al. 2021. Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration. In Proceedings of the 58th Annual Design Automation Conference (DAC).

Digital Library

[6]

Brunno F. Goldstein, et al. 2020. Reliability Evaluation of Compressed Deep Learning Models. In 2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS). 1--5.

[7]

Kaiming He, Xiangyu Zhang, Shaoqing Ren, and Jian Sun. 2016. Deep Residual Learning for Image Recognition. In 2016 IEEE Conference on Computer Vision and Pattern Recognition (CVPR). 770--778.

[8]

Yi He, Prasanna Balaprakash, and Yanjing Li. 2020. FIdelity: Efficient Resilience Analysis Framework for Deep Learning Accelerators. In 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). 270--281.

[9]

Fin Hendrik Bahnsen, Vanessa Klebe, and Goerschwin Fey. 2021. Effect Analysis of Low-Level Hardware Faults on Neural Networks using Emulated Inference. In 2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST). 1--6.

[10]

Endri Kaja, et al. 2021. Extending Verilator to Enable Fault Simulation. In MBMV 2021; 24th Workshop. 1--6.

[11]

Guanpeng Li, et al. 2017. Understanding Error Propagation in Deep Learning Neural Network (DNN) Accelerators and Applications. In SC17: International Conference for High Performance Computing, Networking, Storage and Analysis. 1--12.

[12]

Abdulrahman Mahmoud, et al. 2020. PyTorchFI: A Runtime Perturbation Tool for DNNs. In 2020 50th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W). 25--31.

[13]

Brandon Reagen, et al. 2018. Ares: A framework for quantifying the resilience of deep neural networks. In 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC). 1--6.

Digital Library

[14]

Behzad Salami, Osman S. Unsal, and Adrian Cristal Kestelman. 2018. On the Resilience of RTL NN Accelerators: Fault Characterization and Mitigation. In 2018 30th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD). 322--329.

[15]

Vivienne Sze, Yu-Hsin Chen, Tien-Ju Yang, and Joel Emer. 2017. Efficient Processing of Deep Neural Networks: A Tutorial and Survey. https://arxiv.org/abs/1703.09039

[16]

Christian Szegedy, et al. 2015. Going deeper with convolutions. In 2015 IEEE Conference on Computer Vision and Pattern Recognition (CVPR). 1--9.

[17]

Yung-Yu Tsai and Jin-Fu Li. 2021. Evaluating the Impact of Fault-Tolerance Capability of Deep Neural Networks Caused by Faults. In 2021 IEEE 34th International System-on-Chip Conference (SOCC). 272--277.

[18]

Iris Walter, et al. 2021. Embedded Face Recognition for Personalized Services in the Assistive Robotics., 339--350 pages.

Cited By

Mahmoud KNicolici N(2024)ALPRI-FI: A Framework for Early Assessment of Hardware Fault Resiliency of DNN AcceleratorsElectronics10.3390/electronics1316324313:16(3243)Online publication date: 15-Aug-2024
https://doi.org/10.3390/electronics13163243
Mojumder SFriedrich SMatúš EFettweis GLueders MFriedrich MRenke OBlume HHoefer JSchmidt PBecker JGrantz DKock MBenndorf JFasfous NMori PVoegel HAhmadifarsani SKontopoulos LSchlichtmann UBierzynski K(2024)ZuSE-KI-Mobil AI Chip Design Platform: An Overview2024 IEEE Nordic Circuits and Systems Conference (NorCAS)10.1109/NorCAS64408.2024.10752454(1-7)Online publication date: 29-Oct-2024
https://doi.org/10.1109/NorCAS64408.2024.10752454
Hoefer JStammler MKreß FHotfilter THarbaum TBecker J(2024)BayWatch: Leveraging Bayesian Neural Networks for Hardware Fault Tolerance and Monitoring2024 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)10.1109/DFT63277.2024.10753546(1-6)Online publication date: 8-Oct-2024
https://doi.org/10.1109/DFT63277.2024.10753546
Show More Cited By

Index Terms

SiFI-AI: A Fast and Flexible RTL Fault Simulation Framework Tailored for AI Models and Accelerators
1. Computing methodologies
  1. Machine learning
2. Hardware
  1. Robustness
    1. Fault tolerance

Recommendations

Accelerating RTL Fault Simulation through RTL-to-TLM Abstraction
ETS '11: Proceedings of the 2011 Sixteenth IEEE European Test Symposium

Different fault injection techniques based on simulation have been proposed in the past for functional verification of register transfer level (RTL) IP models. They allow designers to model any type of fault and provide the quality of test patterns ...
Fault Injection into VHDL Models: Experimental Validation of a Fault Tolerant Microcomputer System
EDCC-3: Proceedings of the Third European Dependable Computing Conference on Dependable Computing

This work presents a campaign of fault injection to validate the dependability of a fault tolerant microcomputer system. The system is duplex with cold stand-by sparing, parity detection and a watchdog timer. The faults have been injected on a chip-...
Fast RTL Fault Simulation Using Decision Diagrams and Bitwise Set Operations
DFT '11: Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems

Efficient fault simulation algorithms for combinational circuits are known for decades. However, sequential fault simulation which is frequently used in test and fault tolerance applications remains a very time-consuming task, in particular for larger ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

GLSVLSI '23: Proceedings of the Great Lakes Symposium on VLSI 2023

June 2023

731 pages

ISBN:9798400701252

DOI:10.1145/3583781

General Chairs:
Himanshu Thapliyal
University of Tennessee, Knoxville, USA
,
Ronald DeMara
University of Central Florida, USA
,
Program Chairs:
Inna Partin-Vaisband
University of Illinois Chicago, USA
,
Srinivas Katkoori
University of South Florida, USA

Copyright © 2023 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

Sponsors

SIGDA: ACM Special Interest Group on Design Automation

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 05 June 2023

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Funding Sources

Bundesministerium für Bildung und Forschung

Conference

GLSVLSI '23

Sponsor:

SIGDA

GLSVLSI '23: Great Lakes Symposium on VLSI 2023

June 5 - 7, 2023

TN, Knoxville, USA

Acceptance Rates

Overall Acceptance Rate 312 of 1,156 submissions, 27%

Upcoming Conference

GLSVLSI '25

Sponsor:
sigda

Great Lakes Symposium on VLSI 2025

June 30 - July 2, 2025

New Orleans , LA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

4
Total Citations
View Citations
229
Total Downloads

Downloads (Last 12 months)112
Downloads (Last 6 weeks)5

Reflects downloads up to 22 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

Mahmoud KNicolici N(2024)ALPRI-FI: A Framework for Early Assessment of Hardware Fault Resiliency of DNN AcceleratorsElectronics10.3390/electronics1316324313:16(3243)Online publication date: 15-Aug-2024
https://doi.org/10.3390/electronics13163243
Mojumder SFriedrich SMatúš EFettweis GLueders MFriedrich MRenke OBlume HHoefer JSchmidt PBecker JGrantz DKock MBenndorf JFasfous NMori PVoegel HAhmadifarsani SKontopoulos LSchlichtmann UBierzynski K(2024)ZuSE-KI-Mobil AI Chip Design Platform: An Overview2024 IEEE Nordic Circuits and Systems Conference (NorCAS)10.1109/NorCAS64408.2024.10752454(1-7)Online publication date: 29-Oct-2024
https://doi.org/10.1109/NorCAS64408.2024.10752454
Hoefer JStammler MKreß FHotfilter THarbaum TBecker J(2024)BayWatch: Leveraging Bayesian Neural Networks for Hardware Fault Tolerance and Monitoring2024 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)10.1109/DFT63277.2024.10753546(1-6)Online publication date: 8-Oct-2024
https://doi.org/10.1109/DFT63277.2024.10753546
Hotfilter THoefer JMerz PKreß FKempf FHarbaum TBecker J(2023)Leveraging Mixed-Precision CNN Inference for Increased Robustness and Energy Efficiency2023 IEEE 36th International System-on-Chip Conference (SOCC)10.1109/SOCC58585.2023.10256738(1-6)Online publication date: 5-Sep-2023
https://doi.org/10.1109/SOCC58585.2023.10256738

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents