research-article

Cache Interference-aware Task Partitioning for Non-preemptive Real-time Multi-core Systems

Authors:

Andy D. PimentelAuthors Info & Claims

ACM Transactions on Embedded Computing Systems (TECS), Volume 21, Issue 3

Article No.: 28, Pages 1 - 28

https://doi.org/10.1145/3487581

Published: 28 May 2022 Publication History

Abstract

Shared caches in multi-core processors introduce serious difficulties in providing guarantees on the real-time properties of embedded software due to the interaction and the resulting contention in the shared caches. Prior work has studied the schedulability analysis of global scheduling for real-time multi-core systems with shared caches. This article considers another common scheduling paradigm: partitioned scheduling in the presence of shared cache interference. To achieve this, we propose CITTA, a cache interference-aware task partitioning algorithm. We first analyze the shared cache interference between two programs for set-associative instruction and data caches. Then, an integer programming formulation is constructed to calculate the upper bound on cache interference exhibited by a task, which is required by CITTA. We conduct schedulability analysis of CITTA and formally prove its correctness. A set of experiments is performed to evaluate the schedulability performance of CITTA against global EDF scheduling and other greedy partition approaches such as First-fit and Worst-fit over randomly generated tasksets and realistic workloads in embedded systems. Our empirical evaluations show that CITTA outperforms global EDF scheduling and greedy partition approaches in terms of task sets deemed schedulable.

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Cited By

Fischer TFalk H(2024)Shared Cache Analysis Under Preemptive Scheduling2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE58400.2024.10546581(1-6)Online publication date: 25-Mar-2024
https://doi.org/10.23919/DATE58400.2024.10546581
Sun ZZhou ZFu F(2024)Optimizing code allocation for hybrid on-chip memory in IoT systemsIntegration10.1016/j.vlsi.2024.10219597(102195)Online publication date: Jul-2024
https://doi.org/10.1016/j.vlsi.2024.102195
Sun BKloda TGarcia SGracioli GCaccamo M(2024)Minimizing cache usage with fixed-priority and earliest deadline first schedulingReal-Time Systems10.1007/s11241-024-09423-7Online publication date: 28-Jun-2024
https://doi.org/10.1007/s11241-024-09423-7
Show More Cited By

Index Terms

Cache Interference-aware Task Partitioning for Non-preemptive Real-time Multi-core Systems
1. Computer systems organization
  1. Embedded and cyber-physical systems
    1. Embedded systems
      1. Embedded software

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Published In

cover image ACM Transactions on Embedded Computing Systems

ACM Transactions on Embedded Computing Systems Volume 21, Issue 3

May 2022

365 pages

ISSN:1539-9087

EISSN:1558-3465

DOI:10.1145/3530307

Editor:
Tulika Mitra
National University of Singapore, Singapore

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Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 28 May 2022

Online AM: 26 January 2022

Accepted: 01 September 2021

Revised: 01 August 2021

Received: 01 December 2020

Published in TECS Volume 21, Issue 3

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Cited By

Fischer TFalk H(2024)Shared Cache Analysis Under Preemptive Scheduling2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE58400.2024.10546581(1-6)Online publication date: 25-Mar-2024
https://doi.org/10.23919/DATE58400.2024.10546581
Sun ZZhou ZFu F(2024)Optimizing code allocation for hybrid on-chip memory in IoT systemsIntegration10.1016/j.vlsi.2024.10219597(102195)Online publication date: Jul-2024
https://doi.org/10.1016/j.vlsi.2024.102195
Sun BKloda TGarcia SGracioli GCaccamo M(2024)Minimizing cache usage with fixed-priority and earliest deadline first schedulingReal-Time Systems10.1007/s11241-024-09423-7Online publication date: 28-Jun-2024
https://doi.org/10.1007/s11241-024-09423-7
Chen JLoi IFlamand ETagliavini GBenini LRossi D(2023)Scalable Hierarchical Instruction Cache for Ultralow-Power Processors ClustersIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2022.322833631:4(456-469)Online publication date: 1-Apr-2023
https://dl.acm.org/doi/10.1109/TVLSI.2022.3228336
Sun BRoy DKloda TBastoni APellizzoni RCaccamo M(2023)Co-Optimizing Cache Partitioning and Multi-Core Task Scheduling: Exploit Cache Sensitivity or Not?2023 IEEE Real-Time Systems Symposium (RTSS)10.1109/RTSS59052.2023.00028(224-236)Online publication date: 5-Dec-2023
https://doi.org/10.1109/RTSS59052.2023.00028

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