research-article

Open access

qMC: A Formal Model Checking Verification Framework For Superconducting Logic

Authors:

Aswin Gopikanna,

Massoud Pedram,

Shahin NazarianAuthors Info & Claims

GLSVLSI '21: Proceedings of the 2021 Great Lakes Symposium on VLSI

Pages 259 - 264

https://doi.org/10.1145/3453688.3461522

Published: 22 June 2021 Publication History

Abstract

Single flux quantum (SFQ) circuits as an example of superconducting electronics (SCE) have the potential to replace CMOS circuits as they possess a theoretical potential of three orders of magnitude reduction in power accompanied with one order of magnitude higher speed. Despite its benefits, the SCE community lacks a reliable open source formal verification solution. This paper proposes a verification framework called qMC, a model checker for SFQ circuits using formal techniques. qMC offers an automated process that constructs a SystemVerilog testbench consisting of formal assertions to verify the SFQ-specific properties of the circuits and produce system correctness results and counterexamples using model checking (MC). Instead of creating an MC tool from scratch, we have built qMC based on well established open source back-end verification engines for MC of CMOS circuits, including Yosys-SMTBMC and EBMC. qMC allows for properties to be given in SystemVerilog formal assertions, time-limited SystemVerilog assertions, or linear temporal logic (LTL). qMC provides an improvement in terms of verification time and coverage when compared to state-of-the-art semi-formal based SFQ verification frameworks. For instance, verification time for a 4-bit array multiplier is sped up by 19.5x.

Supplemental Material

MP4 File

Presentation Video

Download
13.59 MB

References

[1]

2021. qMC Source Code. https://gitlab.com/arash1902/qmc

[2]

Najwa Abu Bakar and Ali Selamat. 2012. Agent-based model checking verification framework. (2012), 1--4. https://doi.org/10.1109/ICOS.2012.6417649

[3]

M. Batra, A. Malik, and Meenu Dave. 2013. Formal Methods: Benefits, Challenges and Future Direction. Journal of Global Research in Computer Sciences 4 (2013), 21--25.

[4]

Patricia Bouyer. 2009. Model-checking Timed Temporal Logics. Electronic Notes in Theoretical Computer Science 231 (2009), 323--341. https://doi.org/10.1016/j. entcs.2009.02.044 Proceedings of the 5th Workshop on Methods for Modalities.

Digital Library

[5]

E. Fang and T. Van Duzer. 1989. A Josephson integrated circuit simulator (JSIM) for superconductive electronics application.

[6]

Arash Fayyazi, Shahin Nazarian, and Massoud Pedram. 2020. Logic Verification of Ultra-Deep Pipelined Beyond-CMOS Technologies. CoRR abs/2005.13735 (2020). arXiv:2005.13735 https://arxiv.org/abs/2005.13735

[7]

Coenrad Fourie. 2018. Single Flux Quantum Circuit Technology and CAD overview. In 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). 1--6. https://doi.org/10.1145/3240765.3243498

Digital Library

[8]

Andrew M. Haslam, Kurt M. English, Alexander Derrickson, and John F. McDonald. 2019. Automated Verification and Optimization of SFQ Superconducting Circuits. IEEE Access 7 (2019), 22843--22855. https://doi.org/10.1109/ACCESS. 2019.2899873

[9]

W.N.N. Hung, Xiaoyu Song, Guowu Yang, Jin Yang, and M. Perkowski. 2006. Optimal synthesis of multiple output Boolean functions using a set of quantum gates by symbolic reachability analysis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, 9 (2006), 1652--1663. https://doi.org/10.1109/TCAD.2005.858352

Digital Library

[10]

Ahmed Irfan, Alessandro Cimatti, Alberto Griggio, Marco Roveri, and Roberto Sebastiani. 2016. Verilog2SMV: A tool for word-level verification. In 2016 Design, Automation Test in Europe Conference Exhibition (DATE). 1156--1159.

[11]

Naveen Katam, Alireza Shafaei, and Massoud Pedram. 2017. Design of Complex Rapid Single-Flux-Quantum Cells with Application to Logic Synthesis. In 2017 16th International Superconductive Electronics Conference (ISEC). 1--3. https: //doi.org/10.1109/ISEC.2017.8314236

[12]

Naveen Katam, Soheil Nazar Shahsavani, Ting-Ru Lin, Ghasem Pasandi, Alireza Shafaei, and Massoud Pedram. 2017. Sport lab sfq logic circuit benchmark suite. Univ. Southern California, Los Angeles, CA, USA, Tech. Rep (2017).

[13]

Naveen Kumar Katam, Jamil Kawa, and Massoud Pedram. 2019. Challenges and the status of superconducting single flux quantum technology. In 2019 Design, Automation Test in Europe Conference Exhibition (DATE). 1781--1787. https://doi.org/10.23919/DATE.2019.8747356

[14]

Naveen Kumar Katam and Massoud Pedram. 2019. Timing Characterization for Static Timing Analysis of Single Flux Quantum Circuits. IEEE Transactions on Applied Superconductivity 29, 6 (2019), 1--8. https://doi.org/10.1109/TASC.2019. 2891166

[15]

Takahiro Kawaguchi, Kazuyoshi Takagi, and Naofumi Takagi. 2015. A Verification Method for Single-Flux-Quantum Circuits Using Delay-Based Time Frame Model. IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E98.A (12 2015), 2556--2564. https://doi.org/10.1587/transfun.E98.A.2556

[16]

A. Krasniewski. 1993. Logic simulation of RSFQ circuits. IEEE Transactions on Applied Superconductivity 3, 1 (1993), 33--38. https://doi.org/10.1109/77.233410

[17]

Daniel Kroening and Mitra Purandare. [n.d.]. EBMC: Homepage. http://www. cprover.org

[18]

K.K. Likharev and V.K. Semenov. 1991. RSFQ logic/memory family: a new Josephson-junction technology for sub-terahertz-clock-frequency digital systems. IEEE Transactions on Applied Superconductivity 1, 1 (1991), 3--28. https: //doi.org/10.1109/77.80745

[19]

Shahin Nazarian, Arash Fayyazi, and Massoud Pedram. 2019. qCG: A Low-Power Multi-Domain SFQ Logic Design and Verification Framework. In 2019 IEEE 37th International Conference on Computer Design (ICCD). 446--449. https: //doi.org/10.1109/ICCD46524.2019.00069

[20]

Ghasem Pasandi, Alireza Shafaei, and Massoud Pedram. 2018. SFQmap: A Technology Mapping Tool for Single Flux Quantum Logic Circuits. In 2018 IEEE International Symposium on Circuits and Systems (ISCAS). 1--5. https: //doi.org/10.1109/ISCAS.2018.8351603

[21]

Ramy N. Tadros, Arash Fayyazi, Massoud Pedram, and Peter A. Beerel. 2020. SystemVerilog Modeling of SFQ and AQFP Circuits. IEEE Transactions on Applied Superconductivity 30, 2 (2020), 1--13. https://doi.org/10.1109/TASC.2019.2957196

[22]

Georgios Tzimpragos et al. 2020. A Computational Temporal Logic for Supercon-ducting Accelerators. In Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems (Lausanne, Switzerland) (ASPLOS '20). Association for Computing Machinery, New York, NY, USA, 435--448. https://doi.org/10.1145/3373376.3378517

Digital Library

[23]

Clifford Wolf. [n.d.]. Yosys Open SYnthesis Suite. http://www.clifford.at/yosys/.

[24]

Clifford Wolf. 2017. Formal Verification with SymbiYosys and Yosys-SMTBMC. http://www.clifford.at/papers/2017/smtbmc-sby/slides.pdf

[25]

Alvin D. Wong, Kevin Su, Hang Sun, Arash Fayyazi, Massoud Pedram, and Shahin Nazarian. 2019. VeriSFQ: A Semi-formal Verification Framework and Benchmark for Single Flux Quantum Technology. In 20th International Symposium on Quality Electronic Design (ISQED). 224--230. https://doi.org/10.1109/ISQED.2019.8697701

Cited By

Fourie CJackman KDelport JSchindler LHall TFebvre PIwanikow LChen OAyala CYoshikawa NLaw MWeingartner TWang YBeerel PGupta SZha HRazmkhah SKaramuftuoglu MFayyazi ALi MAnnavaram MNazarian SPedram M(2023)Results From the ColdFlux Superconductor Integrated Circuit Design Tool ProjectIEEE Transactions on Applied Superconductivity10.1109/TASC.2023.330638133:8(1-26)Online publication date: Dec-2023
https://doi.org/10.1109/TASC.2023.3306381
Fayyazi AMunir MAthrey SNazarian SPedram M(2023)Formal Verification of Sequential Circuits in Superconducting Single Flux Quantum TechnologiesIEEE Transactions on Applied Superconductivity10.1109/TASC.2023.326561933:5(1-5)Online publication date: Aug-2023
https://doi.org/10.1109/TASC.2023.3265619
Christensen MTzimpragos GKringen HVolk JSherwood THardekopf BJhala RDillig I(2022)PyLSE: a pulse-transfer level language for superconductor electronicsProceedings of the 43rd ACM SIGPLAN International Conference on Programming Language Design and Implementation10.1145/3519939.3523438(671-686)Online publication date: 9-Jun-2022
https://dl.acm.org/doi/10.1145/3519939.3523438
Show More Cited By

Index Terms

qMC: A Formal Model Checking Verification Framework For Superconducting Logic
1. Hardware
  1. Emerging technologies
    1. Quantum technologies
  2. Hardware validation
    1. Functional verification
      1. Model checking

Recommendations

Was it worth the wait? Yes!

A review of the book, "Verification Methodology Manual for SystemVerilog," by Janick Bergeron et al.
Integrating formal verification in an online judge for e-Learning logic circuit design
SIGCSE '12: Proceedings of the 43rd ACM technical symposium on Computer Science Education

This paper investigates the use of formal verification techniques to create online judges that can assist in teaching logic circuit design. Formal verification not only contributes to give an exact assessment about correctness, but also saves the ...
Word level predicate abstraction and refinement for verifying RTL verilog
DAC '05: Proceedings of the 42nd annual Design Automation Conference

Model checking techniques applied to large industrial circuits suffer from the state space explosion problem. A major technique to address this problem is abstraction. The most commonly used abstraction technique for hardware verification is ...

Comments

Information & Contributors

Information

Published In

GLSVLSI '21: Proceedings of the 2021 Great Lakes Symposium on VLSI

June 2021

504 pages

ISBN:9781450383936

DOI:10.1145/3453688

General Chairs:
Yiran Chen
Duke University, USA
,
Victor Zhirnov
Semiconductor Research Corporation, USA
,
Program Chairs:
Avesta Sasan
George Mason University, USA
,
Ioannis Savidis
Drexel University, USA

Copyright © 2021 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

SIGDA: ACM Special Interest Group on Design Automation

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 22 June 2021

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Data Availability

Presentation Video https://dl.acm.org/doi/10.1145/3453688.3461522#GLSVLSI21-glsv038p.mp4

Funding Sources

Office of the Director of National Intelligence (ODNI), Intelligence Advanced Research Projects Activity (IARPA)

Conference

GLSVLSI '21

Sponsor:

SIGDA

GLSVLSI '21: Great Lakes Symposium on VLSI 2021

June 22 - 25, 2021

Virtual Event, USA

Acceptance Rates

Overall Acceptance Rate 312 of 1,156 submissions, 27%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

4
Total Citations
View Citations
425
Total Downloads

Downloads (Last 12 months)144
Downloads (Last 6 weeks)27

Reflects downloads up to 28 Dec 2024

Other Metrics

View Author Metrics

Citations

Cited By

Fourie CJackman KDelport JSchindler LHall TFebvre PIwanikow LChen OAyala CYoshikawa NLaw MWeingartner TWang YBeerel PGupta SZha HRazmkhah SKaramuftuoglu MFayyazi ALi MAnnavaram MNazarian SPedram M(2023)Results From the ColdFlux Superconductor Integrated Circuit Design Tool ProjectIEEE Transactions on Applied Superconductivity10.1109/TASC.2023.330638133:8(1-26)Online publication date: Dec-2023
https://doi.org/10.1109/TASC.2023.3306381
Fayyazi AMunir MAthrey SNazarian SPedram M(2023)Formal Verification of Sequential Circuits in Superconducting Single Flux Quantum TechnologiesIEEE Transactions on Applied Superconductivity10.1109/TASC.2023.326561933:5(1-5)Online publication date: Aug-2023
https://doi.org/10.1109/TASC.2023.3265619
Christensen MTzimpragos GKringen HVolk JSherwood THardekopf BJhala RDillig I(2022)PyLSE: a pulse-transfer level language for superconductor electronicsProceedings of the 43rd ACM SIGPLAN International Conference on Programming Language Design and Implementation10.1145/3519939.3523438(671-686)Online publication date: 9-Jun-2022
https://dl.acm.org/doi/10.1145/3519939.3523438
Huang JFu RYe XFan D(2022)A survey on superconducting computing technology: circuits, architectures and design toolsCCF Transactions on High Performance Computing10.1007/s42514-022-00089-w4:1(1-22)Online publication date: 16-Mar-2022
https://doi.org/10.1007/s42514-022-00089-w

View Options

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

Media

Figures

Other

Tables

View Table of Contents