Triggered Scheduling: Efficient Detection of Dataflow Network Idleness on Heterogeneous Systems

Hardware-software codesign for FPGAs requires flexible and changeable boundaries between hardware and software. Design space exploration is facilitated by expressing programs in a language that can be compiled for both CPU and FPGA execution. Such an approach requires efficient and general communication mechanisms between hardware and software. We present a practical solution to this problem for heterogeneous programs expressed in CAL, an actor based language running on a PCIe-based FPGA system where communication between a processor and FPGA is relatively expensive. We show how a network of continuously executing software and hardware actors with fine-grained communication can be expressed as a coprocessor model that executes the network in discrete steps with efficient coarse-grained transfers across the PCIe bus.

To this end, we present the Triggered Scheduling (TS) algorithm to detect idleness (i.e. lack of forward progress) of a dynamic actor network with unpredictable consumption/production rates. With TS, it is possible to treat a network of actors running on hardware as a coprocessor that can be called by software. We show how TS can be used to build a truly heterogeneous system on a HLS platform. Using 4 large benchmarks, we analyze the performance and resource utilization of the Triggered Scheduling algorithm.