Article

Free access

A scalable approach to thread-level speculation

Authors:

J. Greggory Steffan,

Christopher B. Colohan,

Todd C. MowryAuthors Info & Claims

ISCA '00: Proceedings of the 27th annual international symposium on Computer architecture

Pages 1 - 12

https://doi.org/10.1145/339647.339650

Published: 01 May 2000 Publication History

Abstract

While architects understand how to build cost-effective parallel machines across a wide spectrum of machine sizes (ranging from within a single chip to large-scale servers), the real challenge is how to easily create parallel software to effectively exploit all of this raw performance potential. One promising technique for overcoming this problem is Thread-Level Speculation (TLS), which enables the compiler to optimistically create parallel threads despite uncertainty as to whether those threads are actually independent. In this paper, we propose and evaluate a design for supporting TLS that seamlessly scales to any machine size because it is a straightforward extension of writeback invalidation-based cache coherence (which itself scales both up and down). Our experimental results demonstrate that our scheme performs well on both single-chip multiprocessors and on larger-scale machines where communication latencies are twenty times larger.

References

[1]

A. V. Aho, R. Sethi, and J. D. Ullman. Compilers: Principles, Techniques and Tools. Addison Wesley, 1986.]]

Digital Library

[2]

H. Akkary and M. Driscoll. A Dynamic Multithreading Processor. In MICRO-31, December 1998.]]

Digital Library

[3]

C. Amza, S. Dwarkadas Ai. Cox, and W. Zwaenepoel. Software DSM Protocols that Adapt between Single Writer and Multiple Writer. In Proceedings of the Third High Performance Computer Architecture Conference, pages 261-271, February 1997.]]

Digital Library

[4]

J.B. Carter, J.K. Bennett, and W. Zwaenepoel. Techniques for reducing consistency-related information in distributed shared memory systems. ACM Transactions on Computer Systems, 13(3):205-243, August 1995.]]

Digital Library

[5]

M. Cintra, J. F. Martinez, and J. Torrellas. Architectural Support for Scalable Speculative Parallelization in Shared-Memory Multiprocessors. In Proceedings oflSCA 27, June 2000.]]

Digital Library

[6]

M. Franklin and G. S. Sohi. ARB: A Hardware Mechanism for Dynamic Reordering of Memory References. IEEE Transactions on Computers, 45(5), May 1996.]]

Digital Library

[7]

S. Gopal, T. Vijaykumar, J. Smith, and G. Sohi. Speculative Versioning Cache. In Proceedings of the Fourth International Symposium on High-Performance Computer Architecture, February 1998.]]

Digital Library

[8]

M. Gupta and R. Nim. Techniques for Speculative Run-Time Parallelization of Loops. In Supercomputing '98, November 1998.]]

Digital Library

[9]

L. Hammond, M. Willey, and K. Olukotun. Data Speculation Support for a Chip Multiprocessor. In Proceedings ofASPLOS-VIII, October 1998.]]

Digital Library

[10]

J. Kahle. Power4: A Dual-CPU Processor Chip. Microprocessor Forum '99, October 1999.]]

[11]

R Keleher, A. L. Cox, S. Dwarkadas, and W. Zwaenepoel. Tread- Marks: Distributed Shared Memory on Standard Workstations and Operating Systems. In Proceedings of the Winter Usenix Conference, January 1994.]]

Digital Library

[12]

T. Knight. An Architecture for Mostly Functional Languages. In Proceedings of the ACM Lisp and Functional Programming Conference, pages 500-519, August 1986.]]

Digital Library

[13]

V. Krishnan and J. Torrellas. The Need for Fast Communication in Hardware-Based Speculative Chip Multiprocessors. In International Conference on Parallel Architectures and Compilation Techniques (PACT), October 1999.]]

Digital Library

[14]

J. Laudon and D. Lenoski. The SGI Origin: A ccNUMA Highly Scalable Server. In Proceedings of the 24th ISCA, pages 241-251, June 1997.]]

Digital Library

[15]

R Marcuello and A. Gonzlez. Clustered Speculative Multithreaded Processors. In Proc. of the ACM Int. Conf. on Supercomputing, June 1999.]]

Digital Library

[16]

K. Olukotun, B. A. Nayfeh, L. Hammond, K. Wilson, and K. Chang. The Case for a Single-Chip Multiprocessor. In Proceedings of ASPLOS- VII, October 1996.]]

Digital Library

[17]

J. Oplinger, D. Heine, and M. S. Lam. In Search of Speculative Thread-Level Parallelism. In Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques (PACT'99), October 1999.]]

Digital Library

[18]

G. S. Sohi, S. Breach, and T. N. Vijaykumar. Multiscalar Processors. In Proceedings of ISCA 22, pages 414-425, June 1995.]]

Digital Library

[19]

J. G. Steffan, C. B. Colohan, and T. C. Mowry. Architectural Support for Thread-Level Data Speculation. Technical Report CMU-CS- 97-188, School of Computer Science, Carnegie Mellon University, November 1997.]]

[20]

J. G. Steffan and T. C. Mowry. The Potential for Using Thread- Level Data Speculation to Facilitate Automatic Parallellization. In Proceedings of the Fourth International Symposium on High- Performance Computer Architecture, February 1998.]]

Digital Library

[21]

M. Tremblay. MAJC: Microprocessor Architecture for Java Computing. HotChips '99, August 1999.]]

[22]

J.-Y. Tsai, J. Huang, C. Amlo, D.J. Lilja, and R-C. Yew. The Superthreaded Processor Architecture. IEEE Transactions on Computers, Special Issue on Multithreaded Architectures, 48(9), September 1999.]]

Digital Library

[23]

D. M. Tullsen, S. J. Eggers, and H. M. Levy. Simultaneous Multithreading: Maximizing On-Chip Parallelism. In Proceedings oflSCA 22, pages 392-403, June 1995.]]

Digital Library

[24]

K. Yeager. The MIPS R10000 superscalar microprocessor. IEEE Micro, April 1996.]]

Digital Library

[25]

Y. Zhang, L. Rauchwerger, and J. Torrellas. Hardware for Speculative Parallelization of Partially-Parallel Loops in DSM Multiprocessors. In Fifth International Symposium on High-Pe~ormance Computer Architecture (HPCA), pages 135-141, January 1999.]]

Digital Library

Cited By

Posluns GZhu YZhang GJeffrey MSalapura VZahran MChong FTang L(2022)A scalable architecture for reprioritizing ordered parallelismProceedings of the 49th Annual International Symposium on Computer Architecture10.1145/3470496.3527387(437-453)Online publication date: 18-Jun-2022
https://dl.acm.org/doi/10.1145/3470496.3527387
Salamanca J(2022)Performance Comparison of Speculative Taskloop and OpenMP-for-Loop Thread-Level Speculation on Hardware Transactional Memory2022 21st International Symposium on Parallel and Distributed Computing (ISPDC)10.1109/ISPDC55340.2022.00021(83-90)Online publication date: Jul-2022
https://doi.org/10.1109/ISPDC55340.2022.00021
Olukotun KHammond LLaudon JOlukotun KHammond LLaudon J(2022)Improving Latency AutomaticallyChip Multiprocessor Architecture10.1007/978-3-031-01720-9_3(61-101)Online publication date: 5-Mar-2022
https://doi.org/10.1007/978-3-031-01720-9_3
Show More Cited By

Index Terms

A scalable approach to thread-level speculation
1. Hardware
  1. Hardware test
  2. Hardware validation
2. Software and its engineering
  1. Software organization and properties
    1. Contextual software domains
      1. Operating systems
        Process management

Recommendations

A scalable approach to thread-level speculation
Special Issue: Proceedings of the 27th annual international symposium on Computer architecture (ISCA '00)

While architects understand how to build cost-effective parallel machines across a wide spectrum of machine sizes (ranging from within a single chip to large-scale servers), the real challenge is how to easily create parallel software to effectively ...
The STAMPede approach to thread-level speculation

Multithreaded processor architectures are becoming increasingly commonplace: many current and upcoming designs support chip multiprocessing, simultaneous multithreading, or both. While it is relatively straightforward to use these architectures to ...
Energy-Efficient Thread-Level Speculation

Chip multiprocessors with thread-level speculation have become the subject of intense research. This work refutes the claim that such a design is necessarily too energy inefficient. In addition, it proposes out-of-order task spawning to exploit more ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

ISCA '00: Proceedings of the 27th annual international symposium on Computer architecture

June 2000

327 pages

ISBN:1581132328

DOI:10.1145/339647

Chairmen:
Alan Berenbaum
Lucent Technologies
,
Joel Emer
Compaq Computer Corp.

ACM SIGARCH Computer Architecture News Volume 28, Issue 2
Special Issue: Proceedings of the 27th annual international symposium on Computer architecture (ISCA '00)
May 2000
325 pages
ISSN:0163-5964
DOI:10.1145/342001
Chairmen:
Alan Berenbaum
Lucent Technologies, Berkeley Heights, NJ
,
Joel Emer
Compaq Computer Corp., Palo Alto, CA
Issue’s Table of Contents

Copyright © 2000 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

SIGARCH: ACM Special Interest Group on Computer Architecture

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 May 2000

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

ISCA00

Sponsor:

SIGARCH

ISCA00: 27th International Symposium on Computer Architecture

British Columbia, Vancouver, Canada

Acceptance Rates

Overall Acceptance Rate 543 of 3,203 submissions, 17%

Upcoming Conference

ISCA '25

Sponsor:
sigarch

The 52nd Annual International Symposium on Computer Architecture

June 21 - 25, 2025

Tokyo , Japan

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

277
Total Citations
View Citations
1,673
Total Downloads

Downloads (Last 12 months)120
Downloads (Last 6 weeks)26

Reflects downloads up to 14 Sep 2024

Other Metrics

View Author Metrics

Citations

Cited By

Posluns GZhu YZhang GJeffrey MSalapura VZahran MChong FTang L(2022)A scalable architecture for reprioritizing ordered parallelismProceedings of the 49th Annual International Symposium on Computer Architecture10.1145/3470496.3527387(437-453)Online publication date: 18-Jun-2022
https://dl.acm.org/doi/10.1145/3470496.3527387
Salamanca J(2022)Performance Comparison of Speculative Taskloop and OpenMP-for-Loop Thread-Level Speculation on Hardware Transactional Memory2022 21st International Symposium on Parallel and Distributed Computing (ISPDC)10.1109/ISPDC55340.2022.00021(83-90)Online publication date: Jul-2022
https://doi.org/10.1109/ISPDC55340.2022.00021
Olukotun KHammond LLaudon JOlukotun KHammond LLaudon J(2022)Improving Latency AutomaticallyChip Multiprocessor Architecture10.1007/978-3-031-01720-9_3(61-101)Online publication date: 5-Mar-2022
https://doi.org/10.1007/978-3-031-01720-9_3
Ahmad MShan MRehman AKhan OAyguadé EHwu WBadia RHofstee H(2020)Accelerating relax-ordered task-parallel workloads using multi-level dependency checkingProceedings of the 34th ACM International Conference on Supercomputing10.1145/3392717.3392758(1-11)Online publication date: 29-Jun-2020
https://dl.acm.org/doi/10.1145/3392717.3392758
Qin CZhu HXu TZhu CMa CChen EXiong H(2020)An Enhanced Neural Network Approach to Person-Job Fit in Talent RecruitmentACM Transactions on Information Systems10.1145/337692738:2(1-33)Online publication date: 11-Feb-2020
https://dl.acm.org/doi/10.1145/3376927
Ying VJeffrey MSanchez D(2020)T4: Compiling Sequential Code for Effective Speculative Parallelization in Hardware2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA)10.1109/ISCA45697.2020.00024(159-172)Online publication date: May-2020
https://doi.org/10.1109/ISCA45697.2020.00024
Saad MPalmieri RRavindran B(2019)LernaACM Transactions on Storage10.1145/331036815:1(1-24)Online publication date: 22-Mar-2019
https://dl.acm.org/doi/10.1145/3310368
Boroumand AGhose SPatel MHassan HLucia BAusavarungnirun RHsieh KHajinazar NMalladi KZheng HMutlu OManne SHunter HAltman E(2019)CoNDAProceedings of the 46th International Symposium on Computer Architecture10.1145/3307650.3322266(629-642)Online publication date: 22-Jun-2019
https://dl.acm.org/doi/10.1145/3307650.3322266
Quadrana MCremonesi PJannach D(2018)Sequence-Aware Recommender SystemsACM Computing Surveys10.1145/319061651:4(1-36)Online publication date: 6-Jul-2018
https://dl.acm.org/doi/10.1145/3190616
Salamanca JAmaral JAraujo G(2018)Using Hardware-Transactional-Memory Support to Implement Thread-Level SpeculationIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2017.275216929:2(466-480)Online publication date: 1-Feb-2018
https://dl.acm.org/doi/10.1109/TPDS.2017.2752169
Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

Media

Figures

Other

Tables

View Table of Contents