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Optimizing Data Plane Programs for the Network

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Mira MeziniAuthors Info & Claims

NetPL'19: Proceedings of the ACM SIGCOMM 2019 Workshop on Networking and Programming Languages

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https://doi.org/10.1145/3341561.3349590

Published: 14 August 2019 Publication History

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Abstract

With the move of Software-defined networking from fixed to programmable data planes, network functions are written with P4 or eBPF for targets such as programmable switches, CPU based flow processors [5] and commodity CPUs [7]. These data plane programs are, however, limited in per-packet time budget [3] (e.g., 67.2 ns at 10GbE) and program size, making program optimization imperative [6]. Existing approaches focus on optimizing the distribution of flow rules in fixed data planes [4] or they are limited to a single switch [2]. We see great potential in integrating the network topology into program optimization.

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References

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M Liu et al. IncBricks: Toward In-Network Computation with an In-Network Cache (ASPLOS'17).

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Krude JRüth JSchemmel DRath FFolbort IWehrle KCarle GOtt J(2021)Determination of throughput guarantees for processor-based SmartNICsProceedings of the 17th International Conference on emerging Networking EXperiments and Technologies10.1145/3485983.3494842(267-281)Online publication date: 2-Dec-2021
https://dl.acm.org/doi/10.1145/3485983.3494842

Index Terms

Optimizing Data Plane Programs for the Network
1. Networks
  1. Network services
    1. Programmable networks

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NetPL'19: Proceedings of the ACM SIGCOMM 2019 Workshop on Networking and Programming Languages

August 2019

9 pages

ISBN:9781450368773

DOI:10.1145/3341561

Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

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Published: 14 August 2019

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Deutsche Forschungsgemeinschaft

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SIGCOMM '19: ACM SIGCOMM 2019 Conference

August 23, 2019

Beijing, China

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NetPL'19 Paper Acceptance Rate 3 of 3 submissions, 100%;

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Krude JRüth JSchemmel DRath FFolbort IWehrle KCarle GOtt J(2021)Determination of throughput guarantees for processor-based SmartNICsProceedings of the 17th International Conference on emerging Networking EXperiments and Technologies10.1145/3485983.3494842(267-281)Online publication date: 2-Dec-2021
https://dl.acm.org/doi/10.1145/3485983.3494842

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Precise Time-synchronization in the Data-Plane using Programmable Switching ASICs

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Precise Time-synchronization in the Data-Plane using Programmable Switching ASICs

The Programmable Data Plane: Abstractions, Architectures, Algorithms, and Applications

Offloading Virtual Evolved Packet Gateway User Plane Functions to a Programmable ASIC

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