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Parallel algorithms for FPGA placement

Authors:

Malay Haldar,

Anshuman Nayak,

Alok Choudhary,

Prith BanerjeeAuthors Info & Claims

GLSVLSI '00: Proceedings of the 10th Great Lakes symposium on VLSI

Pages 86 - 94

https://doi.org/10.1145/330855.330988

Published: 02 March 2000 Publication History

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Abstract

Fast FPGA CAD tools that produce high quality results has been one of the most important research issues in the FPGA domain. Simulated annealing has been the method of choice for placement. However, simulated annealing is a very compute-intensive method. In our present work we investigate a range of parallelization strategies to speedup simulated annealing with application to placement for FPGA. We present experimental results obtained by applying the different parallelization strategies to the Versatile Place and Route (VPR) Tool, implemented on an SGI Origin shared memory multi-processor and an IBM-SP2 distributed memory multi-processor. The results show the tradeoff between execution time and quality of result for the different parallelization strategies.

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Cited By

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Zhao MXiong YZhang HZheng HYu DShen Z(2025)CoaCAD: Correlation-Assisted Computer-Aided Design for Nonvolatile FPGAsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.341904844:1(144-156)Online publication date: Jan-2025
https://doi.org/10.1109/TCAD.2024.3419048
Zhao MXu FZheng HZhang HXiong YJia ZCai X(2023)Correlation-guided Placement for Nonvolatile FPGAs2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247963(1-6)Online publication date: 9-Jul-2023
https://doi.org/10.1109/DAC56929.2023.10247963
Fricke FWerner AShahin KHuebner M(2018)CGRA Tool Flow for Fast Run-Time ReconfigurationApplied Reconfigurable Computing. Architectures, Tools, and Applications10.1007/978-3-319-78890-6_53(661-672)Online publication date: 8-Apr-2018
https://doi.org/10.1007/978-3-319-78890-6_53
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Index Terms

Parallel algorithms for FPGA placement
1. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis
  2. Integrated circuits
    1. Logic circuits

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Improved algorithms for cell placement and their parallel implementations
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FPGA '12: Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays

This work describes a novel approach to FPGA placement. Most conventional FPGA CAD flow clusters circuits into CLBs prior to placing it. We show that is it possible to achieve 28% and 21% improvement in wirelength and minimum channel width respectively, ...

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Published In

GLSVLSI '00: Proceedings of the 10th Great Lakes symposium on VLSI

March 2000

196 pages

ISBN:1581132514

DOI:10.1145/330855

Chairmen:
Majid Sarrafzadeh
Northwestern Univ., Evanston, IL
,
Prith Banerjee
Northwestern Univ., Evanston, IL
,
Kaushik Roy
Purdue Univ., West Lafayette, IN

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 02 March 2000

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GLSVLSI00: Tenth Great Lakes Symposium on VLSI

March 2 - 4, 2000

Illinois, Chicago, USA

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Zhao MXiong YZhang HZheng HYu DShen Z(2025)CoaCAD: Correlation-Assisted Computer-Aided Design for Nonvolatile FPGAsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.341904844:1(144-156)Online publication date: Jan-2025
https://doi.org/10.1109/TCAD.2024.3419048
Zhao MXu FZheng HZhang HXiong YJia ZCai X(2023)Correlation-guided Placement for Nonvolatile FPGAs2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247963(1-6)Online publication date: 9-Jul-2023
https://doi.org/10.1109/DAC56929.2023.10247963
Fricke FWerner AShahin KHuebner M(2018)CGRA Tool Flow for Fast Run-Time ReconfigurationApplied Reconfigurable Computing. Architectures, Tools, and Applications10.1007/978-3-319-78890-6_53(661-672)Online publication date: 8-Apr-2018
https://doi.org/10.1007/978-3-319-78890-6_53
Wang GStitt GLam HGeorge A(2016)Core-level modeling and frequency prediction for DSP applications on FPGAsInternational Journal of Reconfigurable Computing10.1155/2015/7846722015(7-7)Online publication date: 1-Jan-2016
https://dl.acm.org/doi/10.1155/2015/784672
Rajesh Eswarawaka Pagadala PEswara Reddy BRao T(2016)Parallelization of Simulated Annealing Algorithm for FPGA Placement and RoutingProceedings of Fifth International Conference on Soft Computing for Problem Solving10.1007/978-981-10-0448-3_84(1001-1013)Online publication date: 15-Mar-2016
https://doi.org/10.1007/978-981-10-0448-3_84
Eswarawaka RNoor Mahammad SEswara Reddy B(2015)Genetic annealing with efficient strategies to improve the performance for the NP-hard and routing problemsJournal of Experimental & Theoretical Artificial Intelligence10.1080/0952813X.2015.102062427:6(779-788)Online publication date: 24-Mar-2015
https://doi.org/10.1080/0952813X.2015.1020624
Gharibian FShannon LJamieson P(2014)Identifying and placing heterogeneously-sized cluster groupings based on FPGA placement data2014 24th International Conference on Field Programmable Logic and Applications (FPL)10.1109/FPL.2014.6927479(1-6)Online publication date: Sep-2014
https://doi.org/10.1109/FPL.2014.6927479
Gharibian FShannon LJamieson PChung K(2013)Analyzing System-Level Information’s Correlation to FPGA PlacementACM Transactions on Reconfigurable Technology and Systems10.1145/25019856:3(1-21)Online publication date: 1-Oct-2013
https://dl.acm.org/doi/10.1145/2501985
Ludwin ABetz V(2011)Efficient and Deterministic Parallel Placement for FPGAsACM Transactions on Design Automation of Electronic Systems10.1145/1970353.197035516:3(1-23)Online publication date: 1-Jun-2011
https://dl.acm.org/doi/10.1145/1970353.1970355
Wang CLemieux GWawrzynek JCompton K(2011)Scalable and deterministic timing-driven parallel placement for FPGAsProceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays10.1145/1950413.1950445(153-162)Online publication date: 27-Feb-2011
https://dl.acm.org/doi/10.1145/1950413.1950445
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Improved algorithms for cell placement and their parallel implementations

Novel algorithms for placement and routing and their parallel implementations

Parallel FPGA placement based on individual LUT placement (abstract only)

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Improved algorithms for cell placement and their parallel implementations

Novel algorithms for placement and routing and their parallel implementations

Parallel FPGA placement based on individual LUT placement (abstract only)

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