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A Hybrid Framework for Functional Verification using Reinforcement Learning and Deep Learning

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Shahin NazarianAuthors Info & Claims

GLSVLSI '19: Proceedings of the 2019 Great Lakes Symposium on VLSI

Pages 367 - 370

https://doi.org/10.1145/3299874.3318039

Published: 13 May 2019 Publication History

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Abstract

In this paper, we propose a novel hybrid verification framework (HVF) which uses Reinforcement Learning (RL) and Deep Neural Networks (DNNs) to accelerate the verification of complex systems. More precisely, our HVF incorporates RL to generate all possible sequences of vectors needed to approach a target state as well as the corresponding path to the target state which contains a potential design error. Furthermore, HVF utilizes DNNs to accelerate the verification of complex data paths in the target states. We have tested our framework on several circuits including multi-core designs as well as bus-arbiters and confirmed its significant verification speedup when compared to prior work. For example, HVF provides a total speedup of 4.5x for a quad-core MIPS processor verification.

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Shin H(2024)Robust Learning-to-Rank Algorithm for Bug Discovery in Hardware Verification2024 IEEE 37th International System-on-Chip Conference (SOCC)10.1109/SOCC62300.2024.10737744(1-2)Online publication date: 16-Sep-2024
https://doi.org/10.1109/SOCC62300.2024.10737744
Dinu AOgrutan P(2022)Reinforcement Learning Made Affordable for Hardware Verification EngineersMicromachines10.3390/mi1311188713:11(1887)Online publication date: 1-Nov-2022
https://doi.org/10.3390/mi13111887
Nazarian SBogdan P(2020) S 4 oC: A Self-Optimizing, Self-Adapting Secure System-on-Chip Design Framework to Tackle Unknown Threats — A Network Theoretic, Learning Approach 2020 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS45731.2020.9180687(1-8)Online publication date: Oct-2020
https://doi.org/10.1109/ISCAS45731.2020.9180687
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Index Terms

A Hybrid Framework for Functional Verification using Reinforcement Learning and Deep Learning
1. Hardware
  1. Hardware validation
    1. Functional verification
      1. Semi-formal verification
2. Theory of computation
  1. Theory and algorithms for application domains
    1. Machine learning theory
      1. Reinforcement learning

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Published In

GLSVLSI '19: Proceedings of the 2019 Great Lakes Symposium on VLSI

May 2019

562 pages

ISBN:9781450362528

DOI:10.1145/3299874

General Chairs:
Houman Homayoun
George Mason University, USA
,
Baris Taskin
Drexel University, USA
,
Program Chairs:
Tinoosh Mohsenin
UMBC, USA
,
Weisheng Zhao
Beihang University, China

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Published: 13 May 2019

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GLSVLSI '19: Great Lakes Symposium on VLSI 2019

May 9 - 11, 2019

VA, Tysons Corner, USA

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Shin H(2024)Robust Learning-to-Rank Algorithm for Bug Discovery in Hardware Verification2024 IEEE 37th International System-on-Chip Conference (SOCC)10.1109/SOCC62300.2024.10737744(1-2)Online publication date: 16-Sep-2024
https://doi.org/10.1109/SOCC62300.2024.10737744
Dinu AOgrutan P(2022)Reinforcement Learning Made Affordable for Hardware Verification EngineersMicromachines10.3390/mi1311188713:11(1887)Online publication date: 1-Nov-2022
https://doi.org/10.3390/mi13111887
Nazarian SBogdan P(2020) S 4 oC: A Self-Optimizing, Self-Adapting Secure System-on-Chip Design Framework to Tackle Unknown Threats — A Network Theoretic, Learning Approach 2020 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS45731.2020.9180687(1-8)Online publication date: Oct-2020
https://doi.org/10.1109/ISCAS45731.2020.9180687
Nazarian SFayyazi APedram M(2019)qCG: A Low-Power Multi-Domain SFQ Logic Design and Verification Framework2019 IEEE 37th International Conference on Computer Design (ICCD)10.1109/ICCD46524.2019.00069(446-449)Online publication date: Dec-2019
https://doi.org/10.1109/ICCD46524.2019.00069

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