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Boosting the performance with a data-backup-free programming scheme for TLC-based SSDs

Published: 09 April 2018 Publication History

Abstract

Triple-level-ceil(MLCx3) flash-memory chips are prevalent in current storage markets; however, the growing bit-error-rate and worsen reliability of TLC flash ceils impose challenges on the design of flash storage devices. This problem further exaggerates in the design of a reliable storage system which should be able top support the sudden-power-off-recovery functionalities. To guarantee the data integrity, the backup operation is necessary for supporting the sudden-power-off-recovery function, and it is typically adopted to avoid data corruption before programming TLC flash pages. Usually, the backup process results in a significant overhead and the degradation of programming performance. In contrast to the past work which relies on backup-based or RAID-like approaches to resolve the data integrity issue under any sudden power-off, a data-backup-free programming scheme is proposed to totally remove the needs of costly backup procedures as well as guarantee the data reliability. Our goal is to boost the system performance of TLC-based SSDs without harming the flash reliability. The capability of the proposed design is evaluated by a series of experiments, for which we have very encouraging results. Experimental results show that the proposed design can improve performance and reduce the number of block erasures by up to 78% and 76% respectively when compared to an existing backup-based approach.

References

[1]
Y. Kim A. Gupta and B. Urgaonkar. 2009. DFTL: a flash translation layer Employing demand-based selective caching of page-level address mappings. In ASPLOS.
[2]
N. Joukov A. Traeger, E. Zadok and C. P. Wright. 2008. A nine year study of file system and storage benchmarking. ACM Transactions on Storage (TOS) (2008).
[3]
Amir Ban. 1995. Flash File System. US Patient 5,404,485. In M-Systems.
[4]
L.-P. Chang and T.-W. Kuo. 2002. An Adaptive Striping Architecture for Flash Memory Storage Systems of Embedded Systems. In the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS).
[5]
Y.-H. Chang, J.-W. Hsieh, and T.-W. Kuo. 2010. Improving Flash Wear-Leveling by Proactively Moving Static Data. Computers, IEEE Transactions on (Jan 2010).
[6]
E. Galand S. Toiedo. 2005. Algorithms and Data Structures for Flash Memories. Computer. Surveys (June 2005).
[7]
J. Guo, W. Wen, Y. Z. Li, S. Li, H. Li, and Y. Chen. 2013. DA-RAID-5: A disturb aware data protection technique for NAND flash storage systems. In Design, Automation Test in Europe Conference Exhibition (DATE), 2013. 380--385.
[8]
S. Im and D. Shin. 2011. Flash-Aware RAID Techniques for Dependable and High-Performance Flash Memory SSD. Computers, IEEE Transactions on 60, 1 (Jan 2011), 80--92.
[9]
Y. Zhang J. Guo, J. Yang and Y. Chen. 2013. Low cost power failure protection of MLC NAND flash storage systems with PRAM/DRAM hybrid buffer. (2013), 859--864 pages.
[10]
J.-U. Kang, J.-S. Kim, C. Park, H. Park, and J. Lee. 2007. A multi-channel architecture for high-performance NAND flash-based storage system. Journal of System Architecture 53, 9 (2007), 644 -- 658.
[11]
J. Lee and D. Shin. 2014. Adaptive Paired Page Prebackup Scheme for MLC NAND Flash Memory. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 33, 7 (July 2014), 1110--1114.
[12]
Y. Lee, S. Jungand, and Y. H. Song. 2009. FRA: A Flash-aware Redundancy Array of Flash Storage Devices. In Proceedings of the 7th IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISS '09). ACM, New York, NY, USA, 163--172.
[13]
J. Park, J. Jeong, S. Lee, Y. Song, and J. Kim. 2016. Improving Performance and lifetime of NAND storage systems using relaxed program sequence. In 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC). 1--6.
[14]
K. Park, D.-H. Lee, Y. Woo, G. Lee, J.-H. Lee, and D.-H. Kim. 2009. Reliability and performance enhancement technique for SSD array storage system using RAID mechanism. In Communications and Information Technology, 2009. ISCIT 2009. 9th International Symposium on.
[15]
SanDisk. 2011. 24nm 64Gb eX3 (8LC) 3V NAND Flash Memory Data Sheet. Data Sheet (January 2011).
[16]
SanDisk. 2013. Unexpected Power Loss Protection. Technical Report. SanDisk. http://www.sandisk.com/assets/docs/unexpected

Cited By

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  • (2023)ADAR: Application-Specific Data Allocation and Reprogramming Optimization for 3-D TLC Flash MemoryIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.321039042:6(1824-1837)Online publication date: Jun-2023

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cover image ACM Conferences
SAC '18: Proceedings of the 33rd Annual ACM Symposium on Applied Computing
April 2018
2327 pages
ISBN:9781450351911
DOI:10.1145/3167132
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 09 April 2018

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Author Tags

  1. TLC-based flashmemory
  2. performance
  3. power failures
  4. reliability

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SAC 2018
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SAC 2018: Symposium on Applied Computing
April 9 - 13, 2018
Pau, France

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Overall Acceptance Rate 1,650 of 6,669 submissions, 25%

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  • (2023)ADAR: Application-Specific Data Allocation and Reprogramming Optimization for 3-D TLC Flash MemoryIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.321039042:6(1824-1837)Online publication date: Jun-2023

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