research-article

A Program Interference Error Aware LDPC Scheme for Improving NAND Flash Decoding Performance

Authors:

Changsheng Xie,

Jiguang WanAuthors Info & Claims

ACM Transactions on Embedded Computing Systems (TECS), Volume 16, Issue 5s

Article No.: 141, Pages 1 - 20

https://doi.org/10.1145/3126563

Published: 27 September 2017 Publication History

Abstract

By scaling down to smaller cell size, NAND flash has significantly increased the storage capacity in order to lower the unit cost down. However, the reliability is sacrificed due to much higher raw bit error rates. As a result, conventional error correction codes (ECCs), such as BCH codes, are not sufficient. Low-density parity check (LDPC) codes with stronger error correction capability are adopted in NAND flash to guarantee data reliability. However, read performance using LDPC is poor because of its decoding complexity. It has been found that flash cells with fewer electrons are more prone to program interference errors. As a result, program interference errors show the characteristic of value dependence. This characteristic can be exploited and translated into extra information facilitating the decoding convergence. Motivated by this observation, we propose PEAL: a flash <underline>p</underline>rogram interference <underline>e</underline>rror <underline>a</underline>ware <underline>L</underline>DPC scheme to enhance the decoding performance. PEAL integrates the obtained extra information from the value dependence into the soft-to-hard decision process in LDPC decoding to decrease decoding iterations and improve the decoding convergence speed. Simulation results show that decoding iterations are reduced by up to 69.37% and the decoding convergence speed is improved by up to 2.5×, compared with the normalized min-sum (NMS) algorithm with 2KB information lengths at an approximate raw bit error rate of 11.5 × 10⁻³.

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Cited By

Shanthi GRao KKumar AVali SSravani KHasan MTanuja HYashwanth C(2024)Multi-bit error detection and correction codes implementation using generator-parity check matrices techniqueMicrosystem Technologies10.1007/s00542-024-05786-wOnline publication date: 13-Oct-2024
https://doi.org/10.1007/s00542-024-05786-w
Yu QWu FZhang MZhao YXie C(2022)Improving reliability using phase distribution aware LDPC code for holographic data storageApplied Optics10.1364/AO.46393061:21(6119)Online publication date: 11-Jul-2022
https://doi.org/10.1364/AO.463930
Zhang MWu FDu YLiu WXie C(2019)Pair-Bit Errors Aware LDPC Decoding in MLC NAND Flash MemoryIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.287813238:12(2312-2320)Online publication date: 19-Nov-2019
https://dl.acm.org/doi/10.1109/TCAD.2018.2878132
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Index Terms

A Program Interference Error Aware LDPC Scheme for Improving NAND Flash Decoding Performance
1. Computer systems organization
  1. Dependable and fault-tolerant systems and networks
    1. Redundancy
  2. Embedded and cyber-physical systems
    1. Embedded systems
    2. Robotics

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Published In

cover image ACM Transactions on Embedded Computing Systems

ACM Transactions on Embedded Computing Systems Volume 16, Issue 5s

Special Issue ESWEEK 2017, CASES 2017, CODES + ISSS 2017 and EMSOFT 2017

October 2017

1448 pages

ISSN:1539-9087

EISSN:1558-3465

DOI:10.1145/3145508

Editor:
Sandeep K. Shukla
Indian Institute of Technology, India

Issue’s Table of Contents

Copyright © 2017 ACM.

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 27 September 2017

Accepted: 01 June 2017

Revised: 01 May 2017

Received: 01 April 2017

Published in TECS Volume 16, Issue 5s

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National Natural Science Foundation of China
U.S. National Science Foundation (NSF)
Fundamental Research Funds for the Central Universities
the 111 Project
Key Laboratory of Data Storage System, Ministry of Education
Wuhan Science and Technology Project
Shenzhen basic research project

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Cited By

Shanthi GRao KKumar AVali SSravani KHasan MTanuja HYashwanth C(2024)Multi-bit error detection and correction codes implementation using generator-parity check matrices techniqueMicrosystem Technologies10.1007/s00542-024-05786-wOnline publication date: 13-Oct-2024
https://doi.org/10.1007/s00542-024-05786-w
Yu QWu FZhang MZhao YXie C(2022)Improving reliability using phase distribution aware LDPC code for holographic data storageApplied Optics10.1364/AO.46393061:21(6119)Online publication date: 11-Jul-2022
https://doi.org/10.1364/AO.463930
Zhang MWu FDu YLiu WXie C(2019)Pair-Bit Errors Aware LDPC Decoding in MLC NAND Flash MemoryIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.287813238:12(2312-2320)Online publication date: 19-Nov-2019
https://dl.acm.org/doi/10.1109/TCAD.2018.2878132
Wang YZhang MYang XLi T(2019)A Thermal-Aware Physical Space Reallocation for Open-Channel SSD With 3-D Flash MemoryIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.282144238:4(617-627)Online publication date: Apr-2019
https://doi.org/10.1109/TCAD.2018.2821442
V.S. LP.P. D(2019)A secure regenerating code‐based cloud storage with efficient integrity verificationInternational Journal of Communication Systems10.1002/dac.394832:9Online publication date: 2-Apr-2019
https://doi.org/10.1002/dac.3948
Zhang MWu FChen XDu YLiu WZhao YWan JXie C(2018)RBER aware Multi-Sensing for Improving Read Performance of 3D MLC NAND Flash MemoryIEEE Access10.1109/ACCESS.2018.2873081(1-1)Online publication date: 2018
https://doi.org/10.1109/ACCESS.2018.2873081

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