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Converting a 64b PowerPC processor from CMOS bulk to SOI technology

Authors:

D. Allen,

D. Behrends,

B. StanisicAuthors Info & Claims

DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation Conference

Pages 892 - 897

https://doi.org/10.1145/309847.310094

Published: 01 June 1999 Publication History

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References

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D.Allen, et al,"A 550MHz 64b SOI Processor with Cu Interconnects", ISSCC, 1999.

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F. Assaderaghi, et al, "A 7.9/5.5 psec Room/Low Temperature SOI CMOS," IEDM 97, pp. 415-418.

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T.Drumm, J.Mollen, J.Earl,"Differences in Synthesis Behavior between Bulk and SOI Technologies," International Business Machines Technical Memorandum, 1997

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H. H. Chen and D. D. Ling, "Power supply noise analysis methodology for deep submicron VLSI chip design," in Proceedings 34th Design Automation Conference, pp. 638-643, June 1997.

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Cited By

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Chang SChoi G(2007)Gate-Level Exception Handling Design for Noise Reduction in High-Speed VLSI CircuitsProceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems10.1109/VLSID.2007.88(109-114)Online publication date: 6-Jan-2007
https://dl.acm.org/doi/10.1109/VLSID.2007.88
Allen D(2004)A VLSI design methodology for SOI technology2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573)10.1109/SOI.2004.1391531(5-8)Online publication date: 2004
https://doi.org/10.1109/SOI.2004.1391531
Karandikar SSapatnekar SRabaey J(2001)Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effectProceedings of the 38th annual Design Automation Conference10.1145/378239.378527(377-382)Online publication date: 22-Jun-2001
https://dl.acm.org/doi/10.1145/378239.378527

Index Terms

Converting a 64b PowerPC processor from CMOS bulk to SOI technology
1. Applied computing
  1. Physical sciences and engineering
2. Hardware
  1. Emerging technologies
  2. Very large scale integration design

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Published In

DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation Conference

June 1999

1000 pages

ISBN:1581131097

DOI:10.1145/309847

Editor:
Mary Jane Irwin

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Publication History

Published: 01 June 1999

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June 21 - 25, 1999

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

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Chang SChoi G(2007)Gate-Level Exception Handling Design for Noise Reduction in High-Speed VLSI CircuitsProceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems10.1109/VLSID.2007.88(109-114)Online publication date: 6-Jan-2007
https://dl.acm.org/doi/10.1109/VLSID.2007.88
Allen D(2004)A VLSI design methodology for SOI technology2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573)10.1109/SOI.2004.1391531(5-8)Online publication date: 2004
https://doi.org/10.1109/SOI.2004.1391531
Karandikar SSapatnekar SRabaey J(2001)Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effectProceedings of the 38th annual Design Automation Conference10.1145/378239.378527(377-382)Online publication date: 22-Jun-2001
https://dl.acm.org/doi/10.1145/378239.378527

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