research-article

DReAM: Dynamic Re-arrangement of Address Mapping to Improve the Performance of DRAMs

Authors:

Mohsen Ghasempour,

Jim D. Garside,

Mikel LujánAuthors Info & Claims

MEMSYS '16: Proceedings of the Second International Symposium on Memory Systems

Pages 362 - 373

https://doi.org/10.1145/2989081.2989102

Published: 03 October 2016 Publication History

Abstract

The initial location of data in DRAMs is determined and controlled by the 'address-mapping' and even modern memory controllers use a fixed and run-time-agnostic address mapping. On the other hand, the memory access pattern seen at the memory interface level will dynamically change at run-time. This dynamic nature of memory access pattern and the fixed behavior of address mapping process in DRAM controllers, implied by using a fixed address mapping scheme, means that DRAM performance cannot be exploited efficiently.

DReAM is a novel hardware technique that can detect a workload-specific address mapping at run-time based on the application access pattern which improves the performance of DRAMs. The experimental results show that DReAM outperforms the best evaluated address mapping on average by 9%, for mapping-sensitive workloads, by 2% for mapping-insensitive workloads, and up to 28% across all the workloads. DReAM can be seen as an insurance policy capable of detecting which scenarios are not well served by the predefined address mapping.

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Cited By

Zhao YGao MLiu FHu YWang ZLin HLi JXian HDong HYang TJing NLiang XJiang L(2024)UM-PIM: DRAM-based PIM with Uniform & Shared Memory Space2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA)10.1109/ISCA59077.2024.00053(644-659)Online publication date: 29-Jun-2024
https://doi.org/10.1109/ISCA59077.2024.00053
Kim SHur J(2023)Adaptive Image Size Padding for Load Balancing in System-on-Chip Memory HierarchyElectronics10.3390/electronics1216339312:16(3393)Online publication date: 9-Aug-2023
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Oh BAbeyratne NKim NAhn JDreslinski RMudge T(2023)Rethinking DRAM's Page Mode With STT-MRAMIEEE Transactions on Computers10.1109/TC.2022.320713172:5(1503-1517)Online publication date: 1-May-2023
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DReAM: Dynamic Re-arrangement of Address Mapping to Improve the Performance of DRAMs
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory

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MEMSYS '16: Proceedings of the Second International Symposium on Memory Systems

October 2016

463 pages

ISBN:9781450343053

DOI:10.1145/2989081

General Chair:
Bruce Jacob
University of Maryland

Copyright © 2016 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Published: 03 October 2016

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MEMSYS '16: The Second International Symposium on Memory Systems

October 3 - 6, 2016

VA, Alexandria, USA

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Cited By

Zhao YGao MLiu FHu YWang ZLin HLi JXian HDong HYang TJing NLiang XJiang L(2024)UM-PIM: DRAM-based PIM with Uniform & Shared Memory Space2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA)10.1109/ISCA59077.2024.00053(644-659)Online publication date: 29-Jun-2024
https://doi.org/10.1109/ISCA59077.2024.00053
Kim SHur J(2023)Adaptive Image Size Padding for Load Balancing in System-on-Chip Memory HierarchyElectronics10.3390/electronics1216339312:16(3393)Online publication date: 9-Aug-2023
https://doi.org/10.3390/electronics12163393
Oh BAbeyratne NKim NAhn JDreslinski RMudge T(2023)Rethinking DRAM's Page Mode With STT-MRAMIEEE Transactions on Computers10.1109/TC.2022.320713172:5(1503-1517)Online publication date: 1-May-2023
https://doi.org/10.1109/TC.2022.3207131
Namkoong HKim J(2023)CPR: Correlation-based Page Remapping2023 20th International SoC Design Conference (ISOCC)10.1109/ISOCC59558.2023.10396034(309-310)Online publication date: 25-Oct-2023
https://doi.org/10.1109/ISOCC59558.2023.10396034
Zhang JSwift MLi JFalsafi BFerdman MLu SWenisch T(2022)Software-defined address mapping: a case on 3D memoryProceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3503222.3507774(70-83)Online publication date: 28-Feb-2022
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Li XYuan ZGuan YSun GZhang TWei RNiu D(2022)Flatfish: A Reinforcement Learning Approach for Application-Aware Address MappingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.314620441:11(4758-4770)Online publication date: Nov-2022
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Yazdanbakhsh AMoradifirouzabadi ALi ZKang M(2022)Sparse Attention Acceleration with Synergistic In-Memory Pruning and On-Chip Recomputation2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO56248.2022.00059(744-762)Online publication date: Oct-2022
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