research-article

Reducing control bit overhead for X-masking/X-canceling hybrid architecture via pattern partitioning

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Joon-Sung YangAuthors Info & Claims

DAC '16: Proceedings of the 53rd Annual Design Automation Conference

Article No.: 59, Pages 1 - 6

https://doi.org/10.1145/2897937.2898078

Published: 05 June 2016 Publication History

Abstract

An X-masking scheme prevents unknown (X) values from shifting into an output response compactor, whereas an X-canceling MISR methodology allows X's to enter the compactor, but then cancels them out through selective XORing. However, both approaches require significantly high volume of the control bits to remove X values to generate X-free output signatures. This paper proposes a method to reduce the control bit overhead by combining X-masking and X-canceling methodologies and exploiting the fact that unknown values tend to have high correlation in the scan cells. In this paper, correlation is considered across whole patterns in order to enhance reuse of control bits. The proposed hybrid method of X-canceling and X-masking reduces test time without losing fault coverage. The experimental results show that the proposed method significantly reduces control bits and test time compared to a conventional X-canceling MISR methodology.

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Cited By

Mrugalski GRajski JTyszer JWłodarczak B(2023)X-Masking for Deterministic In-System TestsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.326178142:11(4260-4269)Online publication date: Nov-2023
https://doi.org/10.1109/TCAD.2023.3261781
Wang WWang XWang JXiong NCai SLiu P(2022)Ensuring Cryptography Chips Security by Preventing Scan-Based Side-Channel Attacks With Improved DFT ArchitectureIEEE Transactions on Systems, Man, and Cybernetics: Systems10.1109/TSMC.2020.303687952:3(2009-2023)Online publication date: Mar-2022
https://doi.org/10.1109/TSMC.2020.3036879
Wang WDeng ZWang J(2019)Enhancing Sensor Network Security with Improved Internal Hardware DesignSensors10.3390/s1908175219:8(1752)Online publication date: 12-Apr-2019
https://doi.org/10.3390/s19081752
Show More Cited By

Index Terms

Reducing control bit overhead for X-masking/X-canceling hybrid architecture via pattern partitioning
1. Hardware
  1. Hardware test
  2. Robustness

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cover image ACM Other conferences

DAC '16: Proceedings of the 53rd Annual Design Automation Conference

June 2016

1048 pages

ISBN:9781450342360

DOI:10.1145/2897937

Copyright © 2016 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 05 June 2016

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DAC '16

DAC '16: The 53rd Annual Design Automation Conference 2016

June 5 - 9, 2016

Texas, Austin

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Cited By

Mrugalski GRajski JTyszer JWłodarczak B(2023)X-Masking for Deterministic In-System TestsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.326178142:11(4260-4269)Online publication date: Nov-2023
https://doi.org/10.1109/TCAD.2023.3261781
Wang WWang XWang JXiong NCai SLiu P(2022)Ensuring Cryptography Chips Security by Preventing Scan-Based Side-Channel Attacks With Improved DFT ArchitectureIEEE Transactions on Systems, Man, and Cybernetics: Systems10.1109/TSMC.2020.303687952:3(2009-2023)Online publication date: Mar-2022
https://doi.org/10.1109/TSMC.2020.3036879
Wang WDeng ZWang J(2019)Enhancing Sensor Network Security with Improved Internal Hardware DesignSensors10.3390/s1908175219:8(1752)Online publication date: 12-Apr-2019
https://doi.org/10.3390/s19081752
Chae HYang J(2018)Test cost reduction for X-value elimination by scan slice correlation analysisProceedings of the 55th Annual Design Automation Conference10.1145/3195970.3196127(1-6)Online publication date: 24-Jun-2018
https://dl.acm.org/doi/10.1145/3195970.3196127
Kim SChung JYang J(2018) Mitigating Observability Loss of Toggle-Based X -Masking via Scan Chain Partitioning IEEE Transactions on Computers10.1109/TC.2018.280184767:8(1184-1192)Online publication date: 1-Aug-2018
https://doi.org/10.1109/TC.2018.2801847
Shantagiri PKapur R(2018)Handling Unknown with Blend of Scan and Scan CompressionJournal of Electronic Testing: Theory and Applications10.1007/s10836-018-5717-x34:2(135-146)Online publication date: 1-Apr-2018
https://dl.acm.org/doi/10.1007/s10836-018-5717-x
Lien WLee K(2016)Output bit selection methodology for test response compaction2016 IEEE International Test Conference (ITC)10.1109/TEST.2016.7805873(1-10)Online publication date: Nov-2016
https://doi.org/10.1109/TEST.2016.7805873

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