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Partitioning and optimizing controllers synthesized from hierarchical high-level descriptions

Published: 01 May 1998 Publication History

Abstract

This paper describes methods for partitioning and optimizing controllers described by hierarchical high-level descriptions. The methods utilize the structure of the high-level description, provide flexible exploration of the trade-off between combinational logic and registers to reduce implementation cost, and allow the designer to control the synthesis process. Results are presented using industrial examples.

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cover image ACM Conferences
DAC '98: Proceedings of the 35th annual Design Automation Conference
May 1998
820 pages
ISBN:0897919645
DOI:10.1145/277044
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 May 1998

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  1. intellectual property test
  2. system-on-chip test
  3. testing embedded core

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DAC98: The 35th ACM/IEEE-CAS/EDAC Design Automation Conference
June 15 - 19, 1998
California, San Francisco, USA

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