short-paper

VLIW Code Generation for a Convolutional Network Accelerator

Authors:

Maurice Peemen,

Wisnu Pramadi,

Bart Mesman,

Henk CorporaalAuthors Info & Claims

SCOPES '15: Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems

Pages 117 - 120

https://doi.org/10.1145/2764967.2771928

Published: 01 June 2015 Publication History

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Abstract

This paper presents a compiler flow to map Deep Convolutional Networks (ConvNets) to a highly specialized VLIW accelerator core targeting the low-power embedded market. Earlier works have focused on energy efficient accelerators for this class of algorithms, but none of them provides a complete and practical programming model. Due to the large parameter set of a ConvNet it is essential that the user can abstract from the accelerator architecture and does not have to rely on an error prone and ad-hoc assembly programming model. By using modulo scheduling for software pipelining we demonstrate that our automatic generated code achieves equal or within 5-20% less hardware utilization w.r.t. code written manually by experts. Our compiler removes the huge manual workload to efficiently map ConvNets to an energy-efficient core for the next-generation mobile and wearable devices.

References

[1]

S. Chakradhar, M. Sankaradas, V. Jakkula, and S. Cadambi. A dynamically configurable coprocessor for convolutional neural networks. In ISCA'37, 2010.

Digital Library

Google Scholar

[2]

K. Chellapilla, S. Puri, and P. Simard. High performance convolutional neural networks for document processing. In 10th International Workshop on Frontiers in Handwriting Recognition, 2006.

Google Scholar

[3]

T. Chen, Z. Du, N. Sun, J. Wang, C. Wu, Y. Chen, and O. Temam. Diannao: A small-footprint high-throughput accelerator for ubiquitous machine-learning. In ASPLOS'19, 2014.

Digital Library

Google Scholar

[4]

D. C. Ciresan, U. Meier, J. Masci, L. Maria Gambardella, and J. Schmidhuber. Flexible, high performance convolutional neural networks for image classification. In IJCAI, 2011.

Digital Library

Google Scholar

[5]

C. Farabet, B. Martini, B. Corda, P. Akselrod, E. Culurciello, and Y. LeCun. Neuflow: A runtime reconfigurable dataflow processor for vision. In CVPR Workshop, 2011.

Crossref

Google Scholar

[6]

R. Hameed, W. Qadeer, M. Wachs, O. Azizi, A. Solomatnikov, B. C. Lee, S. Richardson, C. Kozyrakis, and M. Horowitz. Understanding sources of inefficiency in general-purpose chips. In ISCA'37, volume 38, pages 37--47. ACM, 2010.

Digital Library

Google Scholar

[7]

K. Jarrett, K. Kavukcuoglu, M. Ranzato, and Y. LeCun. What is the best multi-stage architecture for object recognition? In IEEE 12th International Conference on Computer Vision, 2009.

Crossref

Google Scholar

[8]

A. Krizhevsky, I. Sutskever, and G. E. Hinton. Imagenet classification with deep convolutional neural networks. In NIPS'25, 2012.

Google Scholar

[9]

H. Larochelle, D. Erhan, A. Courville, J. Bergstra, and Y. Bengio. An empirical evaluation of deep architectures on problems with many factors of variation. In ICML'24, 2007.

Digital Library

Google Scholar

[10]

J. Llosa, A. Gonzalez, E. Ayguade, and M. Valero. Swing module scheduling: a lifetime-sensitive approach. In PACT, 1996.

Digital Library

Google Scholar

[11]

M. Peemen, B. Mesman, and H. Corporaal. A data-reuse aware accelerator for large-scale convolutional networks. In NeuroArch Workshop at ISCA '41, 2014.

Google Scholar

Cited By

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IJzerman JViitanen TJääskeläinen PKultala HLehtonen LPeemen MCorporaal HTakala JMudge TPnevmatikatos D(2018)AivoTTAProceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation10.1145/3229631.3229637(28-37)Online publication date: 15-Jul-2018
https://dl.acm.org/doi/10.1145/3229631.3229637
Peemen MShi RLal SJuurlink BMesman BCorporaal HFanucci LTeich J(2016)The neuro vector engineProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2972182(1604-1609)Online publication date: 14-Mar-2016
https://dl.acm.org/doi/10.5555/2971808.2972182

Index Terms

VLIW Code Generation for a Convolutional Network Accelerator
1. Computer systems organization
  1. Architectures
    1. Other architectures
      1. Heterogeneous (hybrid) systems
2. Software and its engineering
  1. Software notations and tools
    1. Compilers

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Information

Published In

SCOPES '15: Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems

June 2015

147 pages

ISBN:9781450335935

DOI:10.1145/2764967

General Chair:
Henk Corporaal
Eindhoven University of Technology, NL
,
Program Chair:
Sander Stuijk
Eindhoven University of Technology, NL

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

In-Cooperation

EDAA: European Design Automation Association

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 June 2015

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Short-paper
Research
Refereed limited

Conference

SCOPES '15

Sponsor:

SIGBED

SCOPES '15: 18th International Workshop on Software and Compilers for Embedded Systems

June 1 - 3, 2015

Sankt Goar, Germany

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Overall Acceptance Rate 38 of 79 submissions, 48%

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Cited By

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IJzerman JViitanen TJääskeläinen PKultala HLehtonen LPeemen MCorporaal HTakala JMudge TPnevmatikatos D(2018)AivoTTAProceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation10.1145/3229631.3229637(28-37)Online publication date: 15-Jul-2018
https://dl.acm.org/doi/10.1145/3229631.3229637
Peemen MShi RLal SJuurlink BMesman BCorporaal HFanucci LTeich J(2016)The neuro vector engineProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2972182(1604-1609)Online publication date: 14-Mar-2016
https://dl.acm.org/doi/10.5555/2971808.2972182

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