Adaptive Reprogramming for Databases on Heterogeneous Processors
Pages 51 - 55
Abstract
It is clear by now that modern processing hardware gets increasingly heterogeneous, which forces data processing algorithms to care about the underlying hardware. However, current approaches for implementing data intensive operators (e.g., in database systems) either cause enormous programming effort for tuning one algorithm to several processors (the hardware-sensitive way), or do not fully exploit possible performance possibilities because of an abstract operator description (the hardware-oblivious way). In this thesis, we propose an algorithm optimizer, which automatically tunes a hardware-oblivious operator description to the underlying hardware. This way, the DBMS can rewrite its operator code until it runs optimally on the given hardware.
References
[1]
M.-C. Albutiu, A. Kemper, and T. Neumann. Massively parallel sort-merge joins in main memory multi-core database systems. VLDB, 5(10):1064--1075, 2012.
[2]
C. Balkesen, G. Alonso, J. Teubner, and M. T. Özsu. Multi-core, main-memory joins: Sort vs. hash revisited. VLDB, 7(1):85--96, 2013.
[3]
C. Balkesen, J. Teubner, G. Alonso, and M. T. Özsu. Main-memory hash joins on multi-core CPUs: Tuning to the underlying hardware. ICDE, pages 362--373, 2013.
[4]
P. Boncz, S. Manegold, and M. L. Kersten. Optimizing database architecture for the new bottleneck: Memory access. In VLDB, volume 9, pages 231--246. Springer, 1999.
[5]
S. Breß. The design and implementation of CoGaDB: A column-oriented GPU-accelerated DBMS. Datenbank-Spektrum, 2014.
[6]
S. Breß, F. Beier, H. Rauhe, K.-U. Sattler, E. Schallehn, and G. Saake. Efficient co-processor utilization in database query processing. Inf. Sys., 38(8):1084--1096, 2013.
[7]
D. Broneske, S. Breß, M. Heimel, and G. Saake. Toward hardware-sensitive database operations. In EDBT, pages 229--234, 2014.
[8]
D. Broneske, S. Breß, and G. Saake. Database Scan Variants on Modern CPUs: A Performance Study. In IMDM@VLDB, pages 97--111. Springer, 2014.
[9]
K. J. Brown, A. K. S. H. Lee, T. Rompf, H. Chafi, M. Odersky, and K. Olukotun. A heterogeneous parallel framework for domain-specific languages. In PACT, pages 89--100, 2011.
[10]
K. Datta, M. Murphy, V. Volkov, S. Williams, J. Carter, L. Oliker, D. Patterson, J. Shalf, and K. Yelick. Stencil computation optimization and auto-tuning on state-of-the-art multicore architectures. In SC, pages 1--12, 2008.
[11]
A. Deshpande, Z. Ives, and V. Raman. Adaptive Query Processing. FTDB, 1(1):1--140, 2007.
[12]
T. Grosser, A. Groesslinger, and C. Lengauer. Polly - performing polyhedral optimizations on a low-level intermediate representation. Parallel Processing Letters, 22(04), 2012.
[13]
B. He, M. Lu, K. Yang, R. Fang, N. K. Govindaraju, Q. Luo, and P. V. Sander. Relational query co-processing on graphics processors. In TODS, volume 34. pp. 21:1--21:39. ACM, 2009.
[14]
B. He, K. Yang, R. Fang, M. Lu, N. K. Govindaraju, Q. Luo, and P. Sander. Relational joins on graphics processors. In SIGMOD, pages 511--524, 2008.
[15]
J. He, M. Lu, and B. He. Revisiting co-processing for hash joins on the coupled CPU-GPU architecture. VLDB, 6(10):1--14, 2013.
[16]
M. Heimel, M. Saecker, H. Pirk, S. Manegold, and V. Markl. Hardware-oblivious parallelism for in-memory column-stores. VLDB, 6(9):709--720, 2013.
[17]
S. Jha, M. Lu, X. Cheng, B. He, and H. P. Huynh. Improving main memory hash joins on Intel Xeon Phi processors: An experimental approach. VLDB, 8(6), 2015.
[18]
T. Kaldewey, G. Lohman, R. Mueller, and P. Volk. GPU join processing revisited. In DaMoN, pages 55--62. ACM, 2012.
[19]
C. Kim, E. Sedlar, J. Chhugani, T. Kaldewey, A. D. Nguyen, A. D. Blas, V. W. Lee, N. Satish, and P. Dubey. Sort vs. hash revisited: Fast join implementation on modern multi-core CPUs. VLDB, 2(2):1378--1389, 2009.
[20]
Y. Klonatos, C. Koch, T. Rompf, and H. Chafi. Building efficient query engines in a high-level language. VLDB, 7(10):853--864, 2014.
[21]
R. Mueller, J. Teubner, and G. Alonso. Sorting networks on FPGAs. VLDB Journal, 21(1):1--23, June 2011.
[22]
O. Polychroniou and K. A. Ross. High throughput heavy hitter aggregation for modern SIMD processors. In DaMoN, pages 37--42, 2013.
[23]
O. Polychroniou and K. A. Ross. Vectorized bloom filters for advanced SIMD processors. In DaMoN, pages 49--54, 2014.
[24]
K. A. Ross. Selection conditions in main-memory. TODS, 29(1):132--161, 2004.
[25]
B. Rǎducanu, P. Boncz, and M. Zukowski. Micro adaptivity in vectorwise. In SIGMOD, pages 1231--1242, 2013.
[26]
E. A. Sitaridi and K. A. Ross. Optimizing select conditions on GPUs. In DaMoN, pages 22--30, 2013.
[27]
T. Willhalm, Y. Boshmaf, H. Plattner, N. Popovici, A. Zeier, and J. Schaffner. SIMD-Scan: Ultra fast in-memory table scan using on-chip vector processing units. PVLDB, 2(1):385--394, 2009.
[28]
T. Willhalm, I. Oukid, I. Müller, and F. Faerber. Vectorizing database column scans with complex predicates. In ADMS, pages 1--12, 2013.
[29]
S. Zhang, J. He, B. He, and M. Lu. OmniDB: Towards portable and efficient query processing on parallel CPU/GPU architectures. VLDB, 2(1):1374--1377, 2013.
[30]
J. Zhou and K. A. Ross. Implementing database operations using SIMD instructions. In SIGMOD, pages 145--156, 2002.
[31]
M. Zukowski, S. Héman, and P. Boncz. Architecture-conscious hashing. In DaMoN, pages 41--49, 2006.
Index Terms
- Adaptive Reprogramming for Databases on Heterogeneous Processors
Recommendations
Soft vector processors vs FPGA custom hardware: measuring and reducing the gap
FPGA '09: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arraysSoft processors are often used in FPGA-based systems because of their ease-of-use, but for a given computation there is a significant gap in area/performance between a C code implementation executing on a soft processor and a custom FPGA hardware ...
Fine-grain performance scaling of soft vector processors
CASES '09: Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systemsEmbedded systems are often implemented on FPGA devices and 25% of the time include a soft processor--a processor built using the FPGA reprogrammable fabric. Because of their prevalence and flexibility, soft processors are compelling targets for ...
Architecture Considerations for Multi-Format Programmable Video Processors
Many different video processor architectures exist. Its architecture gives a processor strength for a particular application. Hardwired logic yields the best performance/cost, but a programmable processor is important for applications that support ...
Comments
Information & Contributors
Information
Published In
Copyright © 2015 ACM.
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]
Sponsors
Publisher
Association for Computing Machinery
New York, NY, United States
Publication History
Published: 31 May 2015
Check for updates
Author Tags
Qualifiers
- Short-paper
Conference
SIGMOD/PODS'15
Sponsor:
SIGMOD/PODS'15: International Conference on Management of Data
May 31, 2015
Victoria, Melbourne, Australia
Acceptance Rates
SIGMOD '15 PhD Symposium Paper Acceptance Rate 9 of 11 submissions, 82%;
Overall Acceptance Rate 40 of 60 submissions, 67%
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- 0Total Citations
- 191Total Downloads
- Downloads (Last 12 months)3
- Downloads (Last 6 weeks)0
Reflects downloads up to 01 Feb 2025
Other Metrics
Citations
View Options
Login options
Check if you have access through your login credentials or your institution to get full access on this article.
Sign in