research-article

Analytical Clustering Score with Application to Post-Placement Multi-Bit Flip-Flop Merging

Authors:

Iris Hui-Ru JiangAuthors Info & Claims

ISPD '15: Proceedings of the 2015 Symposium on International Symposium on Physical Design

Pages 93 - 100

https://doi.org/10.1145/2717764.2717767

Published: 29 March 2015 Publication History

Abstract

Circuit clustering is usually done through discrete optimizations, with the purpose of circuit size reduction or design-specific cluster formation. Specifically, we are interested in the multi-bit flip-flop (MBFF) design technique for clock power reduction, where all previous works rely on discrete clustering optimizations. For example, INTEGRA was the only existing post-placement MBFF clustering optimizer with a sub-quadratic time complexity. However, it degrades the wirelength severely, especially for realistic designs, which may cancel out the benefits of MBFF clustering. In this paper we enable the formulation of an analytical clustering score in nonlinear programming, where the wirelength objective can be seamlessly integrated. It has sub-quadratic time complexity, reduces the clock power by about 20% as the state-of-the-art techniques, and further reduces the wirelength by about 25%. In addition, the proposed method is promising to be integrated in an in-placement MBFF clustering solver and be applied in other problems which require formulating the clustering score in the objective function.

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Cited By

Nirmaladevi VPrabha A(2018)Design Of Modified Data Driven Clock Gating And Look Ahead Clock Gating For Low PowerInternational Journal of Electrical and Electronics Research10.37391/IJEER.0602046:2(32-36)Online publication date: 25-May-2018
https://doi.org/10.37391/IJEER.060204
Gluzer DWimer S(2017)Probability-Driven Multibit Flip-Flop Integration With Clock GatingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.261400425:3(1173-1177)Online publication date: Mar-2017
https://doi.org/10.1109/TVLSI.2016.2614004
Hsu CHashimoto MLin M(2017)Minimizing detection-to-boosting latency toward low-power error-resilient circuitsIntegration10.1016/j.vlsi.2017.01.00258(236-244)Online publication date: Jun-2017
https://doi.org/10.1016/j.vlsi.2017.01.002
Show More Cited By

Index Terms

Analytical Clustering Score with Application to Post-Placement Multi-Bit Flip-Flop Merging
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Placement
      2. Wire routing

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cover image ACM Conferences

ISPD '15: Proceedings of the 2015 Symposium on International Symposium on Physical Design

March 2015

204 pages

ISBN:9781450333993

DOI:10.1145/2717764

General Chair:
Azadeh Davoodi
University of Wisconsin - Madison
,
Program Chair:
Evangeline Young
The Chinese University of Hong Kong

Copyright © 2015 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 29 March 2015

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Research-article

Funding Sources

Research Fund for the Doctoral Program of Higher Education of China(MoE/RFDP)
Beijing Natural Science Foundation(BJNSF)
National Natural Science Foundation of China(NSFC)

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ISPD'15

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SIGDA

ISPD'15: International Symposium on Physical Design

March 29 - April 1, 2015

California, Monterey, USA

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ISPD '15 Paper Acceptance Rate 14 of 37 submissions, 38%;

Overall Acceptance Rate 62 of 172 submissions, 36%

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ISPD '25

Sponsor:
sigda

International Symposium on Physical Design

March 16 - 19, 2025

Austin , TX , USA

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Cited By

Nirmaladevi VPrabha A(2018)Design Of Modified Data Driven Clock Gating And Look Ahead Clock Gating For Low PowerInternational Journal of Electrical and Electronics Research10.37391/IJEER.0602046:2(32-36)Online publication date: 25-May-2018
https://doi.org/10.37391/IJEER.060204
Gluzer DWimer S(2017)Probability-Driven Multibit Flip-Flop Integration With Clock GatingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.261400425:3(1173-1177)Online publication date: Mar-2017
https://doi.org/10.1109/TVLSI.2016.2614004
Hsu CHashimoto MLin M(2017)Minimizing detection-to-boosting latency toward low-power error-resilient circuitsIntegration10.1016/j.vlsi.2017.01.00258(236-244)Online publication date: Jun-2017
https://doi.org/10.1016/j.vlsi.2017.01.002
Hsu CLin MHashimoto MTaskin BHo T(2016)Latch Clustering for Minimizing Detection-to-Boosting Latency Toward Low-Power Resilient CircuitsProceedings of the 18th System Level Interconnect Prediction Workshop10.1145/2947357.2947364(1-6)Online publication date: 4-Jun-2016
https://dl.acm.org/doi/10.1145/2947357.2947364
Wu GXu YWu DRagupathy MMo YChu C(2016)Flip-flop clustering by weighted K-means algorithmProceedings of the 53rd Annual Design Automation Conference10.1145/2897937.2898025(1-6)Online publication date: 5-Jun-2016
https://dl.acm.org/doi/10.1145/2897937.2898025

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