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An efficient assertion checker for combinational properties

Published: 13 June 1997 Publication History

Abstract

Formally verifying properties of signals in a circuit hasseveral applications in an equivalence checking based formalverification flow.In a hierarchical design, functionalityis divided across blocks.This necessitates the useof constraints on input signals of a block to avoid falsenegatives.Validating such input constraints requires assertionchecking at the outputs of modules generatingthe constrained signals.In this paper, we present anefficient assertion checker for combinational propertieswhich avoids the BDD explosion problem by finding anoptimal intermediate correlation free frontier.It hasbeen successfully used in an industrial setting to uncovera number of bugs.

References

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Y. Matsunaga, "An efficient equivalence checker for combinational circuits," 33rd Design Automation Conference, pp. 629-634, May 1996.
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R. E. Bryant, "Binary decision diagrams and beyond: Enabling technologies for formal verification," 32nd Design Automation Conference, pp. 236-243, June 1995.
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C. L. Berman and L. H. Trevillyan, "Functional comparison of logic design for VLSI circuits," International Conference on Computer Aided Design, pp. 456-459, Nov. 1989.
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R. E. Bryant, "Graph-based algorithms for boolean function manipulation," IEEE Transactions on Computers, pp. 677-691, Aug. 1986.
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G. Hasteer, A. Mathur, and P. Banerjee, "PropCheck: An assertion checker for functional properties," tech. rep., Department of Electrical and Computer Engineering, Northwestern University, Evanston, 1997.
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I. Radivojevic and F. Brewer, "A new symbolic technique for control-dependent scheduling," IEEE Transactions on Computer Aided Design, pp. 45-57, Jan. 1996.

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cover image ACM Conferences
DAC '97: Proceedings of the 34th annual Design Automation Conference
June 1997
788 pages
ISBN:0897919203
DOI:10.1145/266021
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Publication History

Published: 13 June 1997

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DAC97: The 34th Design Automation Conference
June 9 - 13, 1997
California, Anaheim, USA

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DAC '97 Paper Acceptance Rate 139 of 400 submissions, 35%;
Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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