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Tools and methodologies for low power design

Published: 13 June 1997 Publication History

Abstract

Designing for low power has becomeincreasingly important in a wide variety ofapplications, including wireless telephony, mobilecomputing, high performance computing, and highspeed networking. Despite reductions in powersupply voltages, power consumption continues to riseand demands increased support from EDA tools andmethodologies. Various tools have emerged toaddress different levels of the power problem, yetconventional methodologies often focus on the lowleverage aspects. This paper will survey existingcommercial tools used in low power design andpresent them in the context of an architecture focusedlow power design methodology.

References

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Intel Components and Reliability Handbook, pg. 7-l, 1991/1992.
[2]
L. Glasser, D. Dobberpuhl, "The Design and Analysis of VLSI Circuits", Reading, Massachusetts, Addison- Wesley, 1985, pp. 105-106.
[3]
Epic Design Technology's PowerMill, http ://www.epic.com/products.html
[4]
Avanti's ADM, http ://www.anagraminc.com/products/index.html
[5]
Epic Design Technology's AMPS, http ://www.epic.com/products.html
[6]
Epic Design Technology's RailMill, http ://www.epic.com/products.html
[7]
Simplex's Thunder & Ligthning, http ://www. simplex.com/ng/products/tnl
[8]
Mentor's QuickPower, http://www.mentorg.com
[9]
Sente's WattWatcher/Gate, http ://www.powereda.com/wwinfo.htm
[10]
Synopys's DesignPower http ://www. synopsys.com/products/power/power_ds.htm 1#2
[11]
Synopsys' Power Compiler, http ://www. synopsys.com/products/power/power_ds.htm 1#3
[12]
D. Singh, J. Rabaey, M. Pedram, F. Catthoor, S. Rajgopal, N. Sehgal, T. Mozdzen, "Power-conscious CAD tools and methodologies: a perspective," in Proceedings of the IEEE, pp. 570-594, April 1995.
[13]
P. Landman, J. Rabaey, "Architectural Power Analysis: the Dual Bit Type Method", IEEE Transactions on VLSI Systems, pp.173-187, June 1995.
[14]
N. Kumar, S. Katkoori, L. Rader, R. Vemuri, "Profile-Driven Behavioral Synthesis for Low-Power VLSI Systems", IEEE Design and Test of Computers, pp. 70-84, Fall 1995.
[15]
Sente's WattWatcher/Architect, http ://www.powereda.com/wwinfo.htm
[16]
A. Chandrakasan, M. Potkonjak, R. M ehra, J. Rabaey, and R. Brodersen, "Optimizing Power Using Transformations", IEEE Transactions on CAD of Integrated Circuits and Systems, pp. 12-31, January 1995.
[17]
R. Mehra, J. Rabaey, "Behavioral Level Power Estimation and Exploration", Proceedings of the 1994 International Workshop on Low Power Design, pp. 197- 202.
[18]
D. Lidsky, J. Rabaey, "Early Power Exploration - A World Wide Web Application", Proceedings of the 1996 Design Automation Conference, pp. 27 - 32.
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P. Landman, R. Mehra, J. Ra baey, "An Integrated CAD Environment for Low-Power Design", IEEE Design and Test of Computers, pp. 72-82, Summer1996.

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cover image ACM Conferences
DAC '97: Proceedings of the 34th annual Design Automation Conference
June 1997
788 pages
ISBN:0897919203
DOI:10.1145/266021
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 13 June 1997

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