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Parallel breadth-first BDD construction

Published: 21 June 1997 Publication History

Abstract

With the increasing complexity of protocol and circuit designs, formal verification has become an important research area and binary decision diagrams (BDDs) have been shown to be a powerful tool in formal verification. This paper presents a parallel algorithm for BDD construction targeted at shared memory multiprocessors and distributed shared memory systems. This algorithm focuses on improving memory access locality through specialized memory managers and partial breadth-first expansion, and on improving processor utilization through dynamic load balancing. The results on a shared memory system show speedups of over two on four processors and speedups of up to four on eight processors. The measured results clearly identify the main source of bottlenecks and point out some intereeting directions for further improvements.

References

[1]
AMZA, C., Cox, A., DWARKADAS, S., HYAMS, C., LI, Z., AND ZWAENEPOEL, W. Treadmarks: Shared memory computing on networks of workstations. IEEE Computer 29, 2 (Feb 1996), 18-28.
[2]
ASHAR, R., AND CHEONG, M. Efficient breadth-first manipulation of binary decision diagrams. In Proceedings of the International Conference on Computer- Aided Design (November 1994), pp. 622-627.
[3]
BRACE, K., RUDELL, R., AND BRYANT, R. E. Efficient implementation of a BDD package. In Proceedings of the #Tth A CM/IEEE Design Automation Conference (June 1990), pp. 40-45.
[4]
BRGLZZ, F., AND FUJtWARA, H. A neutral netlist of 10 combinational benchmark circuits and a target translator in Fortran. In 1985 International Symposium on Circuits And Systems (1985).
[5]
BRYANT, R. E. Graph-based algorithms for Boolean function manipulation. In IEEE Transactions on Computers (1986), vol. C-35, pp. 8:677--691.
[6]
CHEN, Y.-A., AND BRYANT, R. E. Acv: An arithmetic circuit verifier, in Proceedings of the International Conference on Computer-Aided Design (November 1996), pp. 361-365.
[7]
CHEN, Y.-A., YANG, B., AND BRYANT, R. E. Breadthfirst with depth-first BDD construction: A hybrid approac.h. Tech. Rep. CMU-CS-97-120, School of Computer Science, Carnegie Mellon University, 1997.
[8]
DRECHSLER, R., BECKER, B., AND RUPPERTZ, S. K*BMDs: a new data structure for verification. In Proceedings of European Design and Test Conference (March 1996), pp. 2-8.
[9]
DRECHSLER, R., SARABI, A., THEOBALD, M., BECKER, B., AND PERKOWSKI, M. A. Efficient representation and manipulation of switching functions based on ordered kronecker functional decision diagrams. In Proceedings of the 31st ACM/IEEE Design Automation Conference (June 1994), pp. 415-419.
[10]
GAI, S., REBAUDENGO, M., AND REORDA, M. S. A data parallel algorithm for Boolean function manipulation. In Proceedings of Fifth Symposium on Frontiers of Massively Parallel Computation (February 1995), pp. 28-34.
[11]
HETT, A., FRECHSLER, R., AND BECKER, B. MORE: Alternative Implementation of BDD-Packages by Multi-Operand Synthesis. In Proceedings of the European Design Automation Conference (1996).
[12]
JAIN, J., NAaAYAN, A., COELHO, C., KHATm, S., SANGIOVANNI-VINCENTELLI, A., AND R.K. BRAYTON, M. F. Decomposition techniques for efficient ROBDD construction. In Proceedings of the Formal Methods on Computer-Aided Design (November 1996), pp. 419- 434.
[13]
JHA, S., Lu, Y., MINEA, M., AND CLARKE, E. M. Equivalence checking using abstract BDDs. Submitted to 1997 IEEE International Conference on Computer Design, 1997.
[14]
KIMURA, S., AND CLARKE, S. M. A parallel algorithm for constructing binary decision diagrams. In 1990 IEEE Proceedings of the International Conference on Computer Design (Sept 1990), pp. 220-223.
[15]
LENOSKI, D., LAUDON, J., GHARACHORLOO, K., WE- BER, W., GUPTA, A., HENNESSV, J., HoaowITz, M., AND LAM, M. The Stanford Dash multiprocessor. IEEE Computer 25, 3 (Mar. 1992), 63-79.
[16]
Ocm, H., ISHIURA, N., AND YAJIMA, S. Breadth-first manipulation of SBDD of Boolean functions for vector processing. In Proceedings of the Z8th ACM/IEEE Design Automation Conference (June 1991), pp. 413-416.
[17]
OCHI, H., YASUOKA, K., AND YAJIMA, S. Breadthfirst manipulation of very large binary-decision diagrams. In Proceedings of the International Conference on Computer-Aided Design (November 1993), pp. 48- 55.
[18]
PARASURAM, Y., STABLER, E., AND CHIN, S.-K. Parallel implementation of BDD algorithms using a distributed shared memory. In Proceedings of 27th Hawaii International Conference on Systems Sciences (January 1994), pp. 16-25.
[19]
RANJAN, R. K., SANGHAVI, J. V., BRAYTON, P#. K., AND SANGIOVANNI-VINCENTELLI, A. Decision diagrasns on network of workstations. In 1996 IEEE Proceedings of the International Conference on Computer Design (October 1996).
[20]
RANJAN, R. K., SANGHAVI, J. V., BRAYTON, R. K., AND SANGIOVANNI-VINCENTELLI, A. High performance BDD package based on exploiting memory hierarchy. In Proceedings of the 33rd A CM/IEEE Design Automation Conference (June 1996), pp. 635-640.
[21]
RUDELL, R. Dynamic variable ordering for ordered binary decision diagrams. In Proceedings of the International Conference on Computer-Aided Design (November 1993), pp. 139-144.
[22]
SENTOVICH, E. M., SINGH, K. J., LAVAGNO, L., MOON) C.)MURGAI, R., SALDANHA, A., SAVOJ, H.# STEPHAN, P. a.)BRAYTON, R. K.) AND SANGIOVANNI- VINCENTELLI.) A. L. SIS: A system for sequential circuit synthesis. Tech. Rep. UCB/ERL M92/41, Electronics Research Lab. University of California, May 1992.
[23]
SOTRNETTA, W., AND BREWER, F. Implementation of an efficient parallel BDD pac#ge. In Proceedings of the 33rd A CM/IEEE Design Automation Conference (June 1996), pp. 641--644.
[24]
SUBHLOK, J., AND YANG, B. A new model for integrated nested task and data parallel programming, in Ninth A CM SIGPLAN Symposium on Principles and Practice of Parallel Programming (June 1997). To Appear.

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cover image ACM Conferences
PPOPP '97: Proceedings of the sixth ACM SIGPLAN symposium on Principles and practice of parallel programming
June 1997
287 pages
ISBN:0897919068
DOI:10.1145/263764
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 21 June 1997

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PPoPP97: Principles & Practices of Parallel Programming
June 18 - 21, 1997
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PPOPP '97 Paper Acceptance Rate 26 of 86 submissions, 30%;
Overall Acceptance Rate 230 of 1,014 submissions, 23%

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