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ADHA: automatic data layout framework for heterogeneous architectures

Published: 24 August 2014 Publication History

Abstract

Data layouts play a crucial role in determining the performance of a given application running on a given architecture. Existing parallel programming frameworks for both multicore and heterogeneous systems leave the onus of selecting a data layout to the programmer. Therefore, shifting the burden of data layout selection to optimizing compilers can greatly enhance programmer productivity and application performance. In this work, we introduce ADHA: a two-level hierarchal formulation of the data layout problem for modern heterogeneous architectures. We have created a reference implementation of ADHA in the Heterogeneous Habanero-C (H2C) parallel programming system. ADHA shows significant performance benefits of up to 6.92x compared to manually specified layouts for two benchmark programs running on a CPU+GPU heterogeneous platform.

References

[1]
"CDSC Research Applications." {Online}. Available: http://www.cdsc.ucla.edu/research/.
[2]
"Heterogeneous Habanero-C." {Online}. Available: http://habanero.rice.edu/Heterogeneous+Habanero-C.
[3]
Che et al., "Rodinia: A benchmark suite for heterogeneous computing," ser. ISWC'09, Oct 2009.
[4]
D. Majeti et al., "Compiler Driven Data Layout Transformation for Heterogeneous Platforms," in Proc. HeteroPar, 2013.
[5]
I.-J. Sung et al., "Data layout transformation exploiting memory-level parallelism in structured grid many-core applications," in Proc. of PACT, 2010.

Cited By

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  • (2018)GAIDR: An Efficient Time Series Subsets Retrieval Method for Geo-Distributed Astronomical Data2018 IEEE 20th International Conference on High Performance Computing and Communications; IEEE 16th International Conference on Smart City; IEEE 4th International Conference on Data Science and Systems (HPCC/SmartCity/DSS)10.1109/HPCC/SmartCity/DSS.2018.00065(258-265)Online publication date: Jun-2018
  • (2017)Rewriting System for Profile-Guided Data Layout Transformations on BinariesEuro-Par 2017: Parallel Processing10.1007/978-3-319-64203-1_19(260-272)Online publication date: 1-Aug-2017

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    Published In

    cover image ACM Conferences
    PACT '14: Proceedings of the 23rd international conference on Parallel architectures and compilation
    August 2014
    514 pages
    ISBN:9781450328098
    DOI:10.1145/2628071
    Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

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    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 24 August 2014

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    Author Tags

    1. compilers
    2. data layout
    3. heterogeneous architectures

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    PACT '14
    Sponsor:
    • IFIP WG 10.3
    • SIGARCH
    • IEEE CS TCPP
    • IEEE CS TCAA

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    PACT '14 Paper Acceptance Rate 54 of 144 submissions, 38%;
    Overall Acceptance Rate 121 of 471 submissions, 26%

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    • (2018)GAIDR: An Efficient Time Series Subsets Retrieval Method for Geo-Distributed Astronomical Data2018 IEEE 20th International Conference on High Performance Computing and Communications; IEEE 16th International Conference on Smart City; IEEE 4th International Conference on Data Science and Systems (HPCC/SmartCity/DSS)10.1109/HPCC/SmartCity/DSS.2018.00065(258-265)Online publication date: Jun-2018
    • (2017)Rewriting System for Profile-Guided Data Layout Transformations on BinariesEuro-Par 2017: Parallel Processing10.1007/978-3-319-64203-1_19(260-272)Online publication date: 1-Aug-2017

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