research-article

ePlace: Electrostatics Based Placement Using Nesterov's Method

Authors:

Chin-Chih Chang,

Dennis J-.H. Huang,

Chung-Kuan ChengAuthors Info & Claims

DAC '14: Proceedings of the 51st Annual Design Automation Conference

Pages 1 - 6

https://doi.org/10.1145/2593069.2593133

Published: 01 June 2014 Publication History

Abstract

ePlace is a generalized analytic algorithm to handle large-scale standard-cell and mixed-size placement. We use a novel density function based on electrostatics to remove overlap and Nesterov's method to minimize the nonlinear cost. Steplength is estimated as the inverse of Lipschitz constant, which is determined by our dynamic prediction and backtracking method. An approximated preconditioner is proposed to resolve the difference between large macros and standard cells, while an annealing engine is devised to handle macro legalization followed by placement of standard cells. The above innovations are integrated into our placement prototype ePlace, which outperforms the leading-edge placers on respective standard-cell and mixed-size benchmark suites. Specifically, ePlace produces 2.83%, 4.59% and 7.13% shorter wirelength while runs 3.05×, 2.84× and 1.05× faster than BonnPlace, MAPLE and NTUplace3-unified in average of ISPD 2005, ISPD 2006 and MMS circuits, respectively.

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Cited By

Cheng XZhou JZhang ZYu W(2024)An Analytical GPU-Enabled Framework for the Stacked 3D IC LayoutsJournal of Circuits, Systems and Computers10.1142/S021812662450281533:16Online publication date: 10-Jun-2024
https://doi.org/10.1142/S0218126624502815
Mai JWang JChen YGuo ZJiang XLiang YLin Y(2024)OpenPARF 3.0: Robust Multi-Electrostatics Based FPGA Macro Placement Considering Cascaded Macros Groups and Fence Regions2024 2nd International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA62518.2024.10617535(374-379)Online publication date: 10-May-2024
https://doi.org/10.1109/ISEDA62518.2024.10617535
Wang JZhang XTan ZZhu M(2024)RTplace: A Reinforcement Learning-based Macro Placement Method with ResNet and Transformer2024 9th International Conference on Integrated Circuits and Microsystems (ICICM)10.1109/ICICM63644.2024.10814149(677-681)Online publication date: 25-Oct-2024
https://doi.org/10.1109/ICICM63644.2024.10814149
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ePlace: Electrostatics Based Placement Using Nesterov's Method
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

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ePlace-3D: Electrostatics based Placement for 3D-ICs
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We propose a flat, analytic, mixed-size placement algorithm ePlace-3D for three-dimension integrated circuits (3D-ICs) using nonlinear optimization. Our contributions are (1) electrostatics based 3D density function with globally uniform smoothness (2) ...
ePlace: Electrostatics-Based Placement Using Fast Fourier Transform and Nesterov's Method

We develop a flat, analytic, and nonlinear placement algorithm, ePlace, which is more effective, generalized, simpler, and faster than previous works. Based on the analogy between placement instance and electrostatic system, we develop a novel placement ...
ePlace-MS: Electrostatics-Based Placement for Mixed-Size Circuits
We propose an electrostatics-based placement algorithm for large-scale mixed-size circuits (ePlace-MS). ePlace-MS is generalized, flat, analytic and nonlinear. The density modeling method eDensity is extended to handle the mixed-size placement. We conduct ...

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cover image ACM Other conferences

DAC '14: Proceedings of the 51st Annual Design Automation Conference

June 2014

1249 pages

ISBN:9781450327305

DOI:10.1145/2593069

Copyright © 2014 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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EDAC: Electronic Design Automation Consortium
SIGBED: ACM Special Interest Group on Embedded Systems
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CEDA

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Association for Computing Machinery

New York, NY, United States

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Published: 01 June 2014

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DAC '14

DAC '14: The 51st Annual Design Automation Conference 2014

June 1 - 5, 2014

CA, San Francisco, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Cheng XZhou JZhang ZYu W(2024)An Analytical GPU-Enabled Framework for the Stacked 3D IC LayoutsJournal of Circuits, Systems and Computers10.1142/S021812662450281533:16Online publication date: 10-Jun-2024
https://doi.org/10.1142/S0218126624502815
Mai JWang JChen YGuo ZJiang XLiang YLin Y(2024)OpenPARF 3.0: Robust Multi-Electrostatics Based FPGA Macro Placement Considering Cascaded Macros Groups and Fence Regions2024 2nd International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA62518.2024.10617535(374-379)Online publication date: 10-May-2024
https://doi.org/10.1109/ISEDA62518.2024.10617535
Wang JZhang XTan ZZhu M(2024)RTplace: A Reinforcement Learning-based Macro Placement Method with ResNet and Transformer2024 9th International Conference on Integrated Circuits and Microsystems (ICICM)10.1109/ICICM63644.2024.10814149(677-681)Online publication date: 25-Oct-2024
https://doi.org/10.1109/ICICM63644.2024.10814149
Jin YYang XLu Y(2024)Deep Learning-based Algorithm for Multi-objective Driver Chip Cell Layout Optimization2024 IEEE 7th International Conference on Electronic Information and Communication Technology (ICEICT)10.1109/ICEICT61637.2024.10671092(1369-1374)Online publication date: 31-Jul-2024
https://doi.org/10.1109/ICEICT61637.2024.10671092
Tan ZMu Y(2024)Hierarchical reinforcement learning for chip-macro placement in integrated circuitPattern Recognition Letters10.1016/j.patrec.2024.02.002179(108-114)Online publication date: Mar-2024
https://doi.org/10.1016/j.patrec.2024.02.002
Lai YLiu JTang ZWang BHao JLuo PKrause ABrunskill ECho KEngelhardt BSabato SScarlett J(2023)ChiPFormerProceedings of the 40th International Conference on Machine Learning10.5555/3618408.3619165(18346-18364)Online publication date: 23-Jul-2023
https://dl.acm.org/doi/10.5555/3618408.3619165
Chen ZYao HYin X(2023)Learning a Provably Good Wirelength Model for Analytical Placement2023 International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA59274.2023.10218451(358-363)Online publication date: 8-May-2023
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Ding JLu LFu ZMa JGong MQi YYu W(2023)Clock Aware Low Power Placement2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323626(01-08)Online publication date: 28-Oct-2023
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He ZZuo YJiang JZheng HMa YYu B(2023)OpenDRC: An Efficient Open-Source Design Rule Checking Engine with Hierarchical GPU Acceleration2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247734(1-6)Online publication date: 9-Jul-2023
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