Article

Free access

YARDS: FPGA/MPU hybrid architecture for telecommunication data processing

Authors:

Akihiro Tsutsui,

Toshiaki MiyazakiAuthors Info & Claims

FPGA '97: Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays

Pages 93 - 100

https://doi.org/10.1145/258305.258317

Published: 09 February 1997 Publication History

PDF eReader

Abstract

This paper presents a novel system architecture applicable to high-performance and flexible transport data processing which includes complex protocol operation and a nehvork control algorithm. We developed a new tightly coupled Held Programmable Gate Array (FPGA) and Micro-Processing Unit (MPU) system named. Yet Another Re-Definable System (YARDS). It comprises three programmable devices which equateto high flexibility. These devices are the RISC-type MPU with memories, programmable inter-connection devices, and FPGAs. Using these, this system supports various styles of coupling between the FPGAs and the MPU which are suitable for constructing transport data processing. In this paper, two applications of the systemin the telecommunications field are given. One is an Operation, Administration, and Management (OAM) cell operations on an AsynchronousTransfer Mode (ATM) network. The other is a dynamic configuration protocol enables the updateor changeof the functions of the transport data processing system on-line. This is the first approach applying the FPGA/MPU hybrid system to the telecommunications field.

References

[1]

W. Fischer, et al., "Data Communications Using ArM: Architectures, Protocols, and Resource Management," IEEE Communications Magazine, pp. 24-33, Aug. 1994.

Digital Library

Google Scholar

[2]

A. Iwata, et aL, "ATM Connection and Traffic Management Schemes for Multimedia Intemetworking," Communication of the ACM, Vol. 38, No .2, pp. 73-89, Feb. 1995.

Digital Library

Google Scholar

[3]

W. Fischer, et aL, "Data Communications Using ATM: Architectures, Protocols, and Resource Management," ~ Communications Magazine, pp. 24-33, Aug. 1994.

Digital Library

Google Scholar

[4]

A. Tsutsui, et aL, "Special Purpose FPGA for High-speed Digital Telecommunication Systems," Proc. ICCD95, pp. 486-491, Oct. 1995,

Digital Library

Google Scholar

[5]

A. Tsutsui, et aL, "An Efficient Design Environment and Algorithm for Transport Processing FPGA," Proc. VLSI95, pp. 791-798,1995

Google Scholar

[6]

K. Hayashi, et aL, "Reconfigurable Real-Time Signal Transport System using Custom FPGAs," Proc. ~ FCCM95, pp. 68-75, Apr, 1995.

Digital Library

Google Scholar

[7]

S. Casselman, et aL, "Creation of Hardware Objects in a Reconfigurable Computer," Proc. FPL95, pp. 119-128, Aug. 1995.

Digital Library

Google Scholar

[8]

S. Guccione, "List of FPGA-based Computing Machine," URL=http://www. io.com/~guccioneJHW~st.html

Google Scholar

[9]

S. Churcher, et aL, "XC6200 FastMap Processor Interface," Proe, FPL95, pp. 3643, Aug. 1995.

Digital Library

Google Scholar

[10]

R. Kawamura, et aL, "Fast VP-Bandwidth Management with Distributed Control in ArM Networks," IF, ICE TRANS COM., Vol. E77-B, No. 1, pp. 5-14, Jan. 1994.

Google Scholar

[11]

'Ihe ArM Forum Technical Committee, "rmffie Management Specification Version 4," ATM Fomm/95-0013R6, Jun. 1995,

Google Scholar

[12]

"Digital Cross-Connect Systems in Transport Network Survivability," BeUcore SPECIAL REPORT, SR-NWT-002514, No. 1, Jan. 1993.

Google Scholar

[13]

R. Kawamura, et aL, "Implementation of Self-Healing Functions in AIM Networks Based on Virtual Path Concept," Proe. of INFOCOM95, Apr. 1995.

Digital Library

Google Scholar

Cited By

View all

Shukla SBergmann NBecker J(2006)QUKU: A Fast Run Time Reconfigurable Platform for Image Edge DetectionReconfigurable Computing: Architectures and Applications10.1007/11802839_13(93-98)Online publication date: 2006
https://doi.org/10.1007/11802839_13
Amano HShibata YUno M(2002)Reconfigurable Systems: New Activities in AsiaField-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing10.1007/3-540-44614-1_63(585-594)Online publication date: 12-Apr-2002
https://doi.org/10.1007/3-540-44614-1_63
Miyazaki T(1998)Reconfigurable systems: a surveyProceedings of 1998 Asia and South Pacific Design Automation Conference10.1109/ASPDAC.1998.669520(447-452)Online publication date: 1998
https://doi.org/10.1109/ASPDAC.1998.669520

Index Terms

YARDS: FPGA/MPU hybrid architecture for telecommunication data processing
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Partitioning and floorplanning
  2. Very large scale integration design
    1. Application-specific VLSI designs
2. Networks
  1. Network protocols
    1. Link-layer protocols

Recommendations

ANT-on-YARDs: FPGA/MPU hybrid architecture for telecommunication data processing

This paper presents a novel system architecture that combines tightly coupled field programmable gate arrays (FPGA's) and a microprocessing unit (MPU) that we have developed. This system architecture comprises three main programmable devices which yield ...
Synthesizable Standard Cell FPGA Fabrics Targetable by the Verilog-to-Routing CAD Flow
Special Section on Field Programmable Logic and Applications 2015 and Regular Papers

In this article, we consider implementing field-programmable gate arrays (FPGAs) using a standard cell design methodology and present a framework for the automated generation of synthesizable FPGA fabrics. The open-source Verilog-to-Routing (VTR) FPGA ...
Embedded SoPC Design with Nios II Processor and Verilog Examples

Comments

Information & Contributors

Information

Published In

FPGA '97: Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays

February 1997

174 pages

ISBN:0897918010

DOI:10.1145/258305

Chairman:
Carl Ebeling
Univ. of Washington

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 09 February 1997

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

FPGA97

Sponsor:

SIGDA

FPGA97: 1997 ACM/SIGDA International Symposium on Field Programmable Gate Arrays

February 9 - 11, 1997

California, Monterey, USA

Acceptance Rates

Overall Acceptance Rate 125 of 627 submissions, 20%

Upcoming Conference

FPGA '25

Sponsor:
sigda

The 2025 ACM/SIGDA International Symposium on Field Programmable Gate Arrays

February 27 - March 1, 2025

Monterey , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

3
Total Citations
View Citations
455
Total Downloads

Downloads (Last 12 months)84
Downloads (Last 6 weeks)11

Reflects downloads up to 26 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

View all

Shukla SBergmann NBecker J(2006)QUKU: A Fast Run Time Reconfigurable Platform for Image Edge DetectionReconfigurable Computing: Architectures and Applications10.1007/11802839_13(93-98)Online publication date: 2006
https://doi.org/10.1007/11802839_13
Amano HShibata YUno M(2002)Reconfigurable Systems: New Activities in AsiaField-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing10.1007/3-540-44614-1_63(585-594)Online publication date: 12-Apr-2002
https://doi.org/10.1007/3-540-44614-1_63
Miyazaki T(1998)Reconfigurable systems: a surveyProceedings of 1998 Asia and South Pacific Design Automation Conference10.1109/ASPDAC.1998.669520(447-452)Online publication date: 1998
https://doi.org/10.1109/ASPDAC.1998.669520

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

ANT-on-YARDs: FPGA/MPU hybrid architecture for telecommunication data processing

Synthesizable Standard Cell FPGA Fabrics Targetable by the Verilog-to-Routing CAD Flow

Embedded SoPC Design with Nios II Processor and Verilog Examples

Comments

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Qualifiers

Conference

Acceptance Rates

Upcoming Conference

Other Metrics

Article Metrics

Other Metrics

Cited By

PDF

eReader

Login options

Full Access

Abstract

References

Cited By

Index Terms

Recommendations

ANT-on-YARDs: FPGA/MPU hybrid architecture for telecommunication data processing

Synthesizable Standard Cell FPGA Fabrics Targetable by the Verilog-to-Routing CAD Flow

Embedded SoPC Design with Nios II Processor and Verilog Examples

Comments

Information

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Qualifiers

Conference

Acceptance Rates

Upcoming Conference

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

View options

PDF

eReader

Login options

Full Access

Share

Share this Publication link

Share on social media

Affiliations