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Memory block based scan-BIST architecture for application-dependent FPGA testing

Authors:

Michiko InoueAuthors Info & Claims

FPGA '14: Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays

Pages 85 - 88

https://doi.org/10.1145/2554688.2554764

Published: 26 February 2014 Publication History

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Abstract

This paper presents a scan-based BIST architecture for FPGAs used as application-specific embedded devices for low-volume products. The proposed architecture efficiently utilizes memory blocks, instead of logic elements, to build up BIST components such as LFSR, MISR and scan chains for test points. It also provides enhanced scan functionality for test points and performs a hybrid test application of LOC and enhanced scan to improve delay test quality. Experimental results show that the proposed BIST architecture achieves high delay test quality with efficient resource utilization.

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Cited By

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Hatayama KKajihara SYoneda TYamato YInoue MSato YMiura YOhtake S(2018)DART—A Concept of In-field Testing for Enhancing System DependabilityVLSI Design and Test for Systems Dependability10.1007/978-4-431-56594-9_16(553-577)Online publication date: 21-Jul-2018
https://doi.org/10.1007/978-4-431-56594-9_16

Index Terms

Memory block based scan-BIST architecture for application-dependent FPGA testing
1. Hardware
  1. Hardware test
  2. Robustness

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Published In

FPGA '14: Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays

February 2014

272 pages

ISBN:9781450326711

DOI:10.1145/2554688

General Chair:
Vaughn Betz
University of Toronto, Canada
,
Program Chair:
George A. Constantinides
Imperial College London, UK

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 26 February 2014

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FPGA'14

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SIGDA

FPGA'14: The 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

February 26 - 28, 2014

California, Monterey, USA

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FPGA '14 Paper Acceptance Rate 30 of 110 submissions, 27%;

Overall Acceptance Rate 125 of 627 submissions, 20%

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Cited By

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Hatayama KKajihara SYoneda TYamato YInoue MSato YMiura YOhtake S(2018)DART—A Concept of In-field Testing for Enhancing System DependabilityVLSI Design and Test for Systems Dependability10.1007/978-4-431-56594-9_16(553-577)Online publication date: 21-Jul-2018
https://doi.org/10.1007/978-4-431-56594-9_16

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A Shift-Register Based BIST Architecture for FPGA Global Interconnect Testing and Diagnosis

BIST-Based Delay-Fault Testing in FPGAs

Application Dependent FPGA Testing Method