research-article

Innovative instructions and software model for isolated execution

Authors:

Uday R. SavagaonkarAuthors Info & Claims

HASP '13: Proceedings of the 2nd International Workshop on Hardware and Architectural Support for Security and Privacy

Article No.: 10, Page 1

https://doi.org/10.1145/2487726.2488368

Published: 23 June 2013 Publication History

Abstract

For years the PC community has struggled to provide secure solutions on open platforms. Intel has developed innovative new technology to enable SW developers to develop and deploy secure applications on open platforms. The technology enables applications to execute with confidentiality and integrity in the native OS environment. It does this by providing ISA extensions for generating hardware enforceable containers at a granularity determined by the developer. These containers while opaque to the operating system are managed by the OS. This paper analyzes the threats and attacks to applications. It then describes the ISA extension for generating a HW based container. Finally it describes the programming model of this container.

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Kalutharage CMohan SLiu XChrysoulas C(2025)Enhancing Automotive Intrusion Detection Systems with Capability Hardware Enhanced RISC Instructions-Based Memory ProtectionElectronics10.3390/electronics1403047414:3(474)Online publication date: 24-Jan-2025
https://doi.org/10.3390/electronics14030474
Wang QWang LXu SZhang SShao WMihaljević M(2025)Single-Layer Trainable Neural Network for Secure InferenceIEEE Internet of Things Journal10.1109/JIOT.2024.348019512:3(2968-2978)Online publication date: 1-Feb-2025
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Bruhns IBerndt SSander JEisenbarth T(2024)Slalom at the Carnival: Privacy-preserving Inference with Masks from Public KnowledgeIACR Communications in Cryptology10.62056/akp-49qgxqOnline publication date: 7-Oct-2024
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Published In

HASP '13: Proceedings of the 2nd International Workshop on Hardware and Architectural Support for Security and Privacy

June 2013

77 pages

ISBN:9781450321181

DOI:10.1145/2487726

Conference Chairs:
Ruby Lee
Princeton University
,
Weidong Shi
University of Houston

Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 23 June 2013

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HASP '13

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SIGARCH

HASP '13: The Second Workshop on Hardware and Architectural Support for Security and Privacy

June 23 - 24, 2013

Tel-Aviv, Israel

Acceptance Rates

HASP '13 Paper Acceptance Rate 9 of 13 submissions, 69%;

Overall Acceptance Rate 9 of 13 submissions, 69%

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Kalutharage CMohan SLiu XChrysoulas C(2025)Enhancing Automotive Intrusion Detection Systems with Capability Hardware Enhanced RISC Instructions-Based Memory ProtectionElectronics10.3390/electronics1403047414:3(474)Online publication date: 24-Jan-2025
https://doi.org/10.3390/electronics14030474
Wang QWang LXu SZhang SShao WMihaljević M(2025)Single-Layer Trainable Neural Network for Secure InferenceIEEE Internet of Things Journal10.1109/JIOT.2024.348019512:3(2968-2978)Online publication date: 1-Feb-2025
https://doi.org/10.1109/JIOT.2024.3480195
Bruhns IBerndt SSander JEisenbarth T(2024)Slalom at the Carnival: Privacy-preserving Inference with Masks from Public KnowledgeIACR Communications in Cryptology10.62056/akp-49qgxqOnline publication date: 7-Oct-2024
https://doi.org/10.62056/akp-49qgxq
Moshawrab MAdda MBouzouane AIbrahim HRaad A(2024)Securing Federated Learning: Approaches, Mechanisms and OpportunitiesElectronics10.3390/electronics1318367513:18(3675)Online publication date: 16-Sep-2024
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LI RYAMANA H(2024)Privacy Preserving Function Evaluation Using Lookup Tables with Word-Wise FHEIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.2023EAP1114E107.A:8(1163-1177)Online publication date: 1-Aug-2024
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Cheng POzga WValdez EAhmed SGu ZJamjoom HFranke HBottomley J(2024)Intel TDX Demystified: A Top-Down ApproachACM Computing Surveys10.1145/365259756:9(1-33)Online publication date: 25-Apr-2024
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Dynamic coalescing for 16-bit instructions

Streamlining long latency instructions for seamlessly combined out-of-order and in-order execution

Dynamically Scheduling VLIW Instructions

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