poster

Pipeline template and scheduling algorithm for mapping multiple loop nests on FPGA with limited resources

Authors:

Dong Yazhuo,

Zhan Wu,

Ye XiqingAuthors Info & Claims

GLSVLSI '13: Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI

Pages 343 - 344

https://doi.org/10.1145/2483028.2483134

Published: 02 May 2013 Publication History

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Abstract

There are large numbers of high-level algorithms consisting of multiple loop nests in image compression, pattern recognition and digital signal processing. FPGA provides a convenient and flexible solution to speed up these loop-intensive algorithms. However, FPGA reconfiguration which needs a long time is inevitable when switching between the loop nests. This paper presents a parameterized pipeline template to execute all the loop nests in sequence without FPGA reconfiguration. Five steps are designed to decide the parameters. Experiments show that the pipeline template can achieve a comparative execution cycles for a loop comparing with the special hardware structure.

References

[1]

Shail Aditya, Michael S. Schlansker, "ShiftQ: A buffered interconnect for custom loop accelerators." CASES 2001, pp. 158--167.

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[2]

Vinod Kathail, Shail Aditya, Robert Schreiber, B. Ramakrishna Rau, Darren C. Cronquist, Mukund Sivara-man, "PICO: Automatically Designing Custom Computers." IEEE Computer 35(9), pp. 39--47, 2002.

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Index Terms

Pipeline template and scheduling algorithm for mapping multiple loop nests on FPGA with limited resources
1. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis

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Published In

GLSVLSI '13: Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI

May 2013

368 pages

ISBN:9781450320320

DOI:10.1145/2483028

General Chair:
Jose L. Ayala
Complutense University of Madrid, Spain
,
Program Chairs:
Alex Jones
University of Pittsburgh, USA
,
Patrick Madden
Binghamton University, USA
,
Publications Chair:
Ayse K. Coskun
Boston University, USA

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 02 May 2013

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[email protected]

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Poster

Conference

GLSVLSI'13

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SIGDA

GLSVLSI'13: Great Lakes Symposium on VLSI 2013

May 2 - 3, 2013

Paris, France

Acceptance Rates

GLSVLSI '13 Paper Acceptance Rate 76 of 238 submissions, 32%;

Overall Acceptance Rate 312 of 1,156 submissions, 27%

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