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Efficient parametric yield estimation of analog/mixed-signal circuits via Bayesian model fusion

Published: 05 November 2012 Publication History

Abstract

Parametric yield estimation is one of the most critical-yet-challenging tasks for designing and verifying nanoscale analog and mixed-signal circuits. In this paper, we propose a novel Bayesian model fusion (BMF) technique for efficient parametric yield estimation. Our key idea is to borrow the simulation data from an early stage (e.g., schematic-level simulation) to efficiently estimate the performance distributions at a late stage (e.g., post-layout simulation). BMF statistically models the correlation between early-stage and late-stage performance distributions by Bayesian inference. In addition, a convex optimization is formulated to solve the unknown late-stage performance distributions both accurately and robustly. Several circuit examples designed in a commercial 32 nm CMOS process demonstrate that the proposed BMF technique achieves up to 3.75X runtime speedup over the traditional kernel estimation method.

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cover image ACM Conferences
ICCAD '12: Proceedings of the International Conference on Computer-Aided Design
November 2012
781 pages
ISBN:9781450315739
DOI:10.1145/2429384
  • General Chair:
  • Alan J. Hu
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Published: 05 November 2012

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