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New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing

Published: 01 June 1996 Publication History
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References

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K. D. Boese, A. B. Kahng, G. Robins, "High-Per%rmance Routing Trees With Identified Critical Sinks," Proc. A CM/IEEE Design Automation Conf., 1993, pp. 182-187.
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K. D. Boese, A. B. Kahng, B. A. McCoy, G. Robins, "Fidelity and Near-Optimality of Elmore-Based Routing Constructions," Proc. Proc. IEEE Intl. Co@ Computer-Aided Design, 1993.
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J.J. Cong, K.S. Leung, "Optimal Wiresizing Under Elmore Delay Model," IEEE Trans. on CAD, v. 14 no. 3 (1995) pp. 321-336.
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J.J. Cong, K.S. Leung, D. Zhou, "Performance-driven interconnect design based on distributed RC delay model," Proc. A CM/IEEE Design Automation Conf., 1993 pp. 606-611.
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W.C. Elmore, "The Transient Response of Damped Linear Network with particular Regard to Wideband Amplifiers," J. Applied Physics 19 (1948), pp 55-63.
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T. D. Hodes, B. A. McCoy, G. Robins, "Dynamically- Wiresized Elmore-Based Routing Constructions," Proc. IEEE Intl. Symp. Circuits and Systems, 1994.
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F. K. Hwang, D. S. Richards, P. Winter, "The Steiner Tree Problem," Elsevier Science Publishers, (1992), pp. 213-214.
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M. A. B. Jackson, E. S. Kuh, M. Marek-Sadowska, "Timing- Driven Routing for Building Block Layout," Proc. IEEE Intl. Symp. Circuits and Systems, 1987, pp. 518-519.
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A. B. Kahng, G. Robins, "A New Class of Iterative Steiner Tree Heuristics With Good Performance," IEEE Trans. Computer-Aided Design, 11 (1992), pp. 893-902.
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J. Lillis, C. K. Cheng, T. T. Lin, "Optimal Wire Sizing for Low Power and a Generalized Delay Model," Proc. IEEE Intl. Conf. Computer-Aided Design, 1995.
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J. Lillis, C. K. Cheng, T. T. Lin, C.-Y. Ho, "New Techniques for Performance Driven Routing with Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing," Technical Report ~CS96-469, CSE Dept., UCSD.
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S.S. Sapatnekar, "RC Interconnect Optimization under the Elmore Delay Model," Proc. A CM/IEEE Design Automation Conf., 1994, pp. 387-391.
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A. Vittal, M. Marek-Sadowska, "Minimal Delay Interconnect Design Using Alphabetic Trees," Proc. A CM/IEEE Design Automation Conf., 1994, pp. 392-396.
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L.P.P.P van Ginneken, "Buffer Placement in Distributed RC- tree Networks for Minimal Elmore Delay," Proc. International Symposium on Circuits and Systems, 1990, pp 865- 868.

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      cover image ACM Conferences
      DAC '96: Proceedings of the 33rd annual Design Automation Conference
      June 1996
      839 pages
      ISBN:0897917790
      DOI:10.1145/240518
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