Article

Free access

Synthesis tools for mixed-signal ICs: progress on frontend and backend strategies

Authors:

L. Richard Carley,

Georges G. E. Gielen,

Rob A. Rutenbar,

Willy M. C. SansenAuthors Info & Claims

DAC '96: Proceedings of the 33rd annual Design Automation Conference

Pages 298 - 303

https://doi.org/10.1145/240518.240573

Published: 01 June 1996 Publication History

PDF eReader

References

[1]

R. Harjani, R. Rutenbar, L. Carley, "OASYS: a framework for analog circuit synthesis," IEEE Trans. CAD, Vol. 8, No. 12, pp. 1247-1266, December 1989.

Crossref

Google Scholar

[2]

G. Gielen, K. Swings, W. Sansen, "Open analog synthesis system based on declarative models," chapter 18 in Analog Circuit Design (J. Huijsing, R. van der Plassche and W. Sansen. eds.), Kluwer Academic Publishers, pp. 421-445, 1993.

Google Scholar

[3]

E. Malavasi et al., "A top-down, constraint-driven design methodology for analog integrated circuits," chapter 13 in Analog Circuit Design (J. Huijsing, R. van der Plassche and W. Sansen. eds.), Kluwer Academic Publishers, pp. 285-324, 1993.

Crossref

Google Scholar

[4]

M. Degrauwe, et al., "IDAC: an interactive design tool for analog CMOS circuits," IEEE JSSC, Vol. 22, No. 6, pp. 1106- 1116, December 1987.

Crossref

Google Scholar

[5]

G. Beenker, J. Conway, G. Schrooten, A. Slenter, "Analog CAD for consumer ICs," chapter 15 in "Analog circuit design" Analog Circuit Design (J. Huijsing, R. van der Plassche and W. Sansen. eds.), Kluwer Academic Publishers, pp. 347- 367, 1993.

Google Scholar

[6]

R. Henderson, et al., "A spreadsheet interface for analog design knowledge capture and re-use," Proc. IEEE CICC, 13.3, May 1993.

Google Scholar

[7]

E E1-Turky, E. Perry, "BLADES: an artificial intelligence approach to analog circuit design," IEEE Trans. CAD, Vol. 8, No. 6, pp. 680-692, June 1989.

Crossref

Google Scholar

[8]

H. Koh, C. S6quin, E Gray, "OPASYN: a compiler for CMOS operational amplifiers," IEEE Trans. CAD, Vol. 9, No. 2, pp. 113-125, February 1990.

Digital Library

Google Scholar

[9]

G. Jusuf, E Gray, A. Sangiovanni-Vincentelli, "CADICS - Cyclic analog-to- digital converter synthesis," Proc. ACM/IEEE ICCAD, pp. 286- 289, 1990.

Google Scholar

[10]

G. Gielen, H. Walscharts, W. Sansen, "Analog circuit design optimization based on symbolic simulation and simulated annealing," IEEE JSSC, Vol. 25, No. 3, pp. 707-713, June 1990.

Crossref

Google Scholar

[11]

G. Gielen, W. Sansen, Symbolic Analysis For Automated Design Of Analog Integrated Circuits, Kluwer Academic Publishers, 1991.

Digital Library

Google Scholar

[12]

G. Gielen, H. Walscharts, W. Sansen, "ISAAC: a symbolic simulator for analog integrated circuits," IEEE JSSC, Vol. 24, No. 6, pp. 1587- 1597, Dec. 1989.

Crossref

Google Scholar

[13]

K. Swings, W. Sansen, "DONALD: a workbench for interactive design space exploration and sizing of analog circuits," Proc. EDAC, pp. 475- 479, 1991.

Digital Library

Google Scholar

[14]

K. Swings, W. Sansen, "ARIADNE: a constraint-based approach to computer-aided synthesis and modeling of analog integrated circuits", Kluwer International Journal on Analog Integrated Circuits and Signal Processing, Vol. 3, pp. 197-215, 1993.

Digital Library

Google Scholar

[15]

E Veselinovic, et al., "A flexible topology selection program as part of an analog synthesis system," Proc. ED&TC, pp. 119-123, 1995.

Digital Library

Google Scholar

[16]

G. Gielen, et al., "An analog module generator for mixed analog/digital ASIC design," International Journal of Circuit Theory and Applications, Vol. 23, pp. 269-283, July-August 1995.

Crossref

Google Scholar

[17]

J.E Harvey, et al., "STAIC: An interactive framework for synthesizing CMOS and BiCMOS analog circuits," IEEE Trans. CAD, Vol. 11, No. 11, pp. 1402-1415, Nov. 1992.

Crossref

Google Scholar

[18]

C. Toumazou, C.A. Makris, "Analog IC design automation: Part I -- Automated circuit generation: New concepts and methods," IEEE Trans. CAD, Vol. 14, No. 2, pp. 218-238, Feb. 1995.

Digital Library

Google Scholar

[19]

N. Horta, J. Franca, C. Leme, "Automated high level synthesis of data conversion systems," chapter 17 of Analogue-Digital Asics - Circuit Techniques, Design Tool And Applications (Soin, Maloberti and Franca, eds.), Peter Peregrinus Ltd., 1991.

Google Scholar

[20]

E Medeiro, B. P6rez-Verdfi, A. Rodrfguez-Vfizquez, J. L. Huertas, "A vertically-integrated tool for automated design of SD modulators," Proc. ESSCIRC, pp. 164- 167, 1994.

Google Scholar

[21]

W. Nye, D. Riley, A. Sangiovanni-Vincentelli, A. Tits, "DELIGHT.SPICE: an optimization-based system for the design of integrated circuits," IEEE Trans. CAD, Vol. 7, No. 4, pp. 501-519, April 1988.

Digital Library

Google Scholar

[22]

E Medeiro, et al., "A statistical optimization-based approach for automated sizing of analog cells," Proc. ACM/IEEE ICCAD, pp. 594-597, Nov. 1994.

Digital Library

Google Scholar

[23]

E.S. Ochotta, R.A. Rutenbar, L.R. Carley, "ASTRX/OBLX: Tools for rapid synthesis of high-performance analog circuits," IEEE Trans. CAD, to appear 1996.

Digital Library

Google Scholar

[24]

E.S. Ochotta, L.R. Carley, R.A. Rutenbar "Analog circuit synthesis for large, realistic cells: designing a pipelined A/D converter with ASTRX/OBLX," Proc. IEEE CICC, May 1994.

Crossref

Google Scholar

[25]

H. Onodera, et al., "Operational amplifier compilation with performance optimization," IEEE JSSC, Vol. SC-25, No. 2, pp. 466-473, Apr. 1990.

Google Scholar

[26]

EC. Maulik, L.R. Carley, R.A. Rutenbar "Simultaneous topology selection and sizing of cell-level analog circuits," IEEE Trans. CAD, Vol. 14, No. 4, April 1995.

Digital Library

Google Scholar

[27]

Z.Q. Neng, et al., "SEAS: A simulated evolution approach for analog circuit synthesis," Proc. IEEE CICC, 5.2, May 1991.

Google Scholar

[28]

W. Kruiskamp, D. Leenaerts, "DARWIN: CMOS opamp synthesis by means of a genetic algorithm," Proc. ACM/IEEE DAC, pp. 433-438, June 1995.

Digital Library

Google Scholar

[29]

J. Crols, S. Donnay, M. Steyaert, G. Gielen, "A high-level design and optimization tool for analog RF receiver front-ends," proc. ICCAD, pp. 550-553, 1995.

Digital Library

Google Scholar

[30]

J. Assael, E Senn, M. Tawfik, "A switched-capacitor filter silicon compiler," IEEE Journal of Solid-State Circuits, Vol. 23, No. 1, pp. 166- 174, February 1988.

Crossref

Google Scholar

[31]

T. Mukherjee, L.R. Carley, R.A. Rutenbar, "Synthesis of manufacturable analog circuits," Proc. ACM/IEEE ICCAD, pp. 586-593, Nov. 1995.

Digital Library

Google Scholar

[32]

J. Kuhn, "Analog Module Generators for Silicon Compilation," VLSI Systems Design, May 1987.

Google Scholar

[33]

J. Rijmenants. et al., "ILAC: An automated layout tool for analog cmos circuits," IEEE JSSC, Vol. 24, No. 4, pp. 417-425, April 1989.

Crossref

Google Scholar

[34]

D. J. Garrod, R. A. Rutenbar, L. R. Carley, "Automatic layout of custom analog cells in ANANGRAM", Proc. ICCAD, pp. 544-547, Nov. 1988.

Google Scholar

[35]

J. M. Cohn, D. J. Garrod, R. A. Rutenbar, L. R. Carley, "KOAN/ANA- GRAM II: New tools for device-level analog placement and routing," IEEE JSSC, Vol. 26, No. 3, March, 1991.

Google Scholar

[36]

J.M Cohn, D. J. Garrod, R. A. Rutenbar, L. R. Carley, Analog Device- Level Layout Automation, Kluwer Acad. Publ., 1994.

Digital Library

Google Scholar

[37]

M. Mogaki, et al., "LADIES: An automatic layout system for analog LSI's," Proc. ACM/IEEE ICCAD, pp. 450-453, Nov. 1989.

Google Scholar

[38]

E. Malavasi, et al., "A routing methodology for analog integrated circuits," Proc. ACM/IEEE ICCAD, pp. 202-205, Nov 1990.

Google Scholar

[39]

E. Malavasi, A. Sangiovanni-Vincentelli, "Area routing for analog layout," IEEE Trans. CAD, Vol. 12, No. 8, pp. 1186-1197, Aug, 1993.

Digital Library

Google Scholar

[40]

B. Basaran, R. A. Rutenbar, L. R. Carley, "Latchup-aware placement and parasitic-bounded routing of custom analog cells", Proc. ACM/ IEEE ICCAD, Nov. 1993.

Digital Library

Google Scholar

[41]

K. Lampaert, G. Gielen, W. Sansen, "Analog routing for manufacturability," Proc. IEEE CICC, May 1996.

Google Scholar

[42]

K. Lampaert, G. Gielen, W.M. Sansen, "A performance-driven placement tool for analog integrated circuits," IEEE JSSC, Vol. 30, No. 7, pp. 773-780, July 1995.

Crossref

Google Scholar

[43]

E. Malavasi, D. Pandini, "Optimum CMOS stack generation with analog constraints", IEEE Trans. CAD, Vol. 14, No. 1, pp. 107-12, Jan. 1995.

Digital Library

Google Scholar

[44]

E. Charbon, E. Malavasi, U. Choudhury, A. Casotto, A. Sangiovanni- Vincentelli, "A constraint-driven placement methodology for analog integrated circuits", Proc. IEEE CICC, pp. 28.2/1-4, May 1992.

Google Scholar

[45]

B. Basaran, R. A. Rutenbar, "An O(n) algorithm for transistor stacking with performance constraints", Proc. ACM/IEEE DAC, June 1996.

Digital Library

Google Scholar

[46]

U. Choudhury, A. Sangiovanni-Vincentelli, "Automatic generation of parasitic constraints for performance-constrained physical design of analog circuits", IEEE Trans. CAD, Vol. 12, No. 2, pp. 208-224, February 1993.

Digital Library

Google Scholar

[47]

E. Charbon, E. Malavasi, A. Sangiovanni-Vincentelli, "Generalized constraint generation for analog circuit design", Proc. IEEE/ACM ICCAD, pp. 408-414, Nov. 1993.

Digital Library

Google Scholar

[48]

R. Okuda, T. Sato, H. Onodera, K. Tamuru, "An efficient algorithm for layout compaction problem with symmetry constraints," Proc. IEEE ICCAD, pp. 148-151, Nov. 1989.

Google Scholar

[49]

E. Malavasi, E. Felt, E. Charbon, A. Sangiovanni-Vincentelli, "Symbolic compaction with analog constraints," Int. J. Circuit Theory and Applic., Vol. 23, No. 4, pp. 433-452, Jul/Aug 1995.

Crossref

Google Scholar

[50]

J. Cohn, D. Garrod, R. Rutenbar, L. R. Carley, "Techniques for simultaneous placement and routing of custom analog cells in KOAN/ANA- GRAM II," Proc. ACM/IEEE ICCAD, pp. 394-397, Nov. 1991.

Google Scholar

[51]

R.A. Rutenbar, "Analog design automation: Where are we? Where are we going?" Proc. IEEE CICC, May 1993.

Google Scholar

[52]

H. Yaghutiel, A. Sangiovanni-Vincentelli, E R. Gray, "A methodology for automated layout of switched capacitor filters," in Proc. ACM/IEEE ICCAD, Nov. 1986.

Google Scholar

[53]

C. D. Kimble, et al., "Analog autorouted VLSI," Proc. ACM/IEEE CICC., June 1985.

Google Scholar

[54]

R. S. Gyurcsik, J. C. Jeen, "A generalized approach to routing mixed analog and digital signal nets in a channel," IEEE JSSC, Vol. 24, No. 2, pp. 436-442, Apr. 1989.

Crossref

Google Scholar

[55]

U. Choudhury, A. Sangiovanni-Vincentelli, "Constraint-based channel routing for analog and mixed analog/digital circuits," IEEE Trans. CAD, Vol. 12, No. 4, pp. 497-510, Apr. 1993.

Digital Library

Google Scholar

[56]

S. Mitra, S. Nag, R. A. Rutenbar, and L. R. Carley, "System-level routing of mixed-signal ASICs in WREN," Proc. ACM/IEEE ICCAD, Nov. 1992.

Digital Library

Google Scholar

[57]

S. Mitra, R. A. Rutenbar, L. R. Carley, D.J. Allstot, "Substrate-aware mixed-signal macrocell placement in WRIGHT," IEEE JSSC, Vol. 30, No. 3, pp. 269-278, Mar. 1995.

Crossref

Google Scholar

[58]

B. R. Stanisic, N. K. Verghese, R. A. Rutenbar, L. R. Carley, D. J. Allstot, "Addressing substrate coupling in mixed-mode IC's: simulation and power distribution synthesis", IEEE JSSC, Vol. 29, No. 3, Mar. 1994.

Google Scholar

[59]

N.K. Verghese, D.J. Allstot, T. Schmerbeck, Simulation Techniques and Solutions for Mixed-Signal Integrated Circuits, Kluwer Acad. Pub., 1995.

Digital Library

Google Scholar

[60]

B.R. Stanisic, R.A. Rutenbar, L.R. Carley, Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs, Kluwer Academic Publishers, 1996.

Digital Library

Google Scholar

[61]

L. T. Pillage, R. A. Rohrer, "Asymptotic waveform evaluation for timing analysis", IEEE Trans. CAD, Vol. 9, No. 4, Apr. 1990.

Crossref

Google Scholar

[62]

T. Schmerbeck, R. Richetta, L. Smith, "A 27 MHz mixed analog/digital recording channel DSP using partial response signalling with maximum likelihood detection," in Tech. Digest IEEE ISSCC, Feb. 1991.

Google Scholar

[63]

R. Rutenbar et al., "Synthesis and layout for mixed-signal ics in the acacia system," in Analog Circuit Design, (J.H. Huijsing, R. J. van de Plassche and W.M.C Sansen, eds.), Kluwer Acad. Publishers, pp. 127- 146, 1996.

Digital Library

Google Scholar

[64]

E. Malavasi, E. Felt, E. Charbon and A. Sangiovanni-Vincentelli, "Automation of IC Layout with Analog Constraints," IEEE Trans. CAD, to appear 1996.

Digital Library

Google Scholar

Cited By

View all

Mansour NElnozahi MRagaai H(2022)Parasitic-Aware Simulation-Based Optimization Design Tool for Current Steering VGAsElectronics10.3390/electronics1201013212:1(132)Online publication date: 28-Dec-2022
https://doi.org/10.3390/electronics12010132
Jiao FMontano SFerent CDoboli A(2015)I-Flows: A Novel Approach to Computational Intelligence for Analog Circuit Design Automation Through Symbolic Data Mining and Knowledge-Intensive ReasoningComputational Intelligence in Analog and Mixed-Signal (AMS) and Radio-Frequency (RF) Circuit Design10.1007/978-3-319-19872-9_1(3-28)Online publication date: 15-Jul-2015
https://doi.org/10.1007/978-3-319-19872-9_1
Agarwal AShekhar C(2011)Synthesis of Analog IC Building BlocksProceedings of the 2011 IEEE Computer Society Annual Symposium on VLSI10.1109/ISVLSI.2011.37(361-362)Online publication date: 4-Jul-2011
https://dl.acm.org/doi/10.1109/ISVLSI.2011.37
Show More Cited By

Index Terms

Synthesis tools for mixed-signal ICs: progress on frontend and backend strategies
1. Applied computing
  1. Physical sciences and engineering

Recommendations

Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs
Mixed ptl/static logic synthesis using genetic algorithms: theory and applications
Structure Synthesis of Analog and Mixed-Signal Circuits using Partition Techniques
ISQED '06: Proceedings of the 7th International Symposium on Quality Electronic Design

This paper presents an automatic structure synthesis techniques by partitioning of the analog and mixed-signal circuit models. It translates a behavioral-level analog description written in VHDL-AMS into a structure-level VHDL-AMS specification based on ...

Comments

Information & Contributors

Information

Published In

DAC '96: Proceedings of the 33rd annual Design Automation Conference

June 1996

839 pages

ISBN:0897917790

DOI:10.1145/240518

Chairmen:
Thomas P. Pennino
Bell Labs, Holmdel, NJ
,
Ellen J. Yoffa
IBM Corp., Yorktown Heights, NY

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 June 1996

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

DAC96

Sponsor:

EDAC
SIGDA
IEEE-CAS

DAC96: The 33rd Design Automation Conference

June 3 - 7, 1996

Nevada, Las Vegas, USA

Acceptance Rates

DAC '96 Paper Acceptance Rate 142 of 377 submissions, 38%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

37
Total Citations
View Citations
738
Total Downloads

Downloads (Last 12 months)104
Downloads (Last 6 weeks)12

Reflects downloads up to 28 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

View all

Mansour NElnozahi MRagaai H(2022)Parasitic-Aware Simulation-Based Optimization Design Tool for Current Steering VGAsElectronics10.3390/electronics1201013212:1(132)Online publication date: 28-Dec-2022
https://doi.org/10.3390/electronics12010132
Jiao FMontano SFerent CDoboli A(2015)I-Flows: A Novel Approach to Computational Intelligence for Analog Circuit Design Automation Through Symbolic Data Mining and Knowledge-Intensive ReasoningComputational Intelligence in Analog and Mixed-Signal (AMS) and Radio-Frequency (RF) Circuit Design10.1007/978-3-319-19872-9_1(3-28)Online publication date: 15-Jul-2015
https://doi.org/10.1007/978-3-319-19872-9_1
Agarwal AShekhar C(2011)Synthesis of Analog IC Building BlocksProceedings of the 2011 IEEE Computer Society Annual Symposium on VLSI10.1109/ISVLSI.2011.37(361-362)Online publication date: 4-Jul-2011
https://dl.acm.org/doi/10.1109/ISVLSI.2011.37
Barros MGuilherme JHorta NBarros MGuilherme JHorta N(2010)State-of-the-Art on Analog Design AutomationAnalog Circuits and Systems Optimization based on Evolutionary Computation Techniques10.1007/978-3-642-12346-7_2(19-47)Online publication date: 2010
https://doi.org/10.1007/978-3-642-12346-7_2
Barros MGuilherme JHorta NBarros MGuilherme JHorta N(2010)IntroductionAnalog Circuits and Systems Optimization based on Evolutionary Computation Techniques10.1007/978-3-642-12346-7_1(1-18)Online publication date: 2010
https://doi.org/10.1007/978-3-642-12346-7_1
Martens EGielen G(2009)ANTIGONEIntegration, the VLSI Journal10.1016/j.vlsi.2008.07.00142:1(10-23)Online publication date: 1-Jan-2009
https://dl.acm.org/doi/10.1016/j.vlsi.2008.07.001
Stefanović DKayal M(2008)PAD toolStructured Analog CMOS Design10.1007/978-1-4020-8573-4_6(169-187)Online publication date: 2008
https://doi.org/10.1007/978-1-4020-8573-4_6
Martens EGielen G(2008)Analog and Mixed-Signal Design StrategiesHigh-Level Modeling and Synthesis of Analog Integrated Systems10.1007/978-1-4020-6802-7_3(37-81)Online publication date: 2008
https://doi.org/10.1007/978-1-4020-6802-7_3
Labrak LTixier TFellah YAbouchi N(2007)A new approach for automated analog design optimizationProceedings of the 11th Conference on Proceedings of the 11th WSEAS International Conference on Circuits - Volume 1110.5555/1348610.1348614(17-21)Online publication date: 23-Jul-2007
https://dl.acm.org/doi/10.5555/1348610.1348614
Xu YPileggi LBoyd SMalik SFix LKahng A(2004)ORACLEProceedings of the 41st annual Design Automation Conference10.1145/996566.996611(151-154)Online publication date: 7-Jun-2004
https://dl.acm.org/doi/10.1145/996566.996611
Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs

Mixed ptl/static logic synthesis using genetic algorithms: theory and applications

Structure Synthesis of Analog and Mixed-Signal Circuits using Partition Techniques

Comments

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Qualifiers

Conference

Acceptance Rates

Upcoming Conference

Other Metrics

Article Metrics

Other Metrics

Cited By

PDF

eReader

Login options

Full Access

References

Cited By

Index Terms

Recommendations

Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs

Mixed ptl/static logic synthesis using genetic algorithms: theory and applications

Structure Synthesis of Analog and Mixed-Signal Circuits using Partition Techniques

Comments

Information

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Qualifiers

Conference

Acceptance Rates

Upcoming Conference

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

View options

PDF

eReader

Login options

Full Access

Share

Share this Publication link

Share on social media

Affiliations