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Resource augmentation for fault-tolerance feasibility of real-time tasks under error bursts

Published: 08 November 2012 Publication History

Abstract

Dependability is a vital system requirement, particularly in safety critical and mission critical real-time systems, due to the potentially catastrophic consequences of failures. In most critical applications different fault tolerance mechanisms using redundancy are employed to prevent possible failures. In the case of real-time systems the system designer must ensure that the task set is feasible even under faults, which we refer to as 'fault tolerance feasibility'. Due to cost considerations, often temporal redundancy has been prevalently used to meet this objective.
In this paper we focus on guaranteeing fault-tolerance feasibility under error bursts on uni-processor systems by the usage of resource augmentation, specifically through processor speed-up. Firstly, we derive a processor demand bound based sufficient condition for a set of real-time tasks to be fault tolerance feasible under an assumption that no more than one error burst occurs during the hyper-period of the task set. Subsequently, we derive the necessary resource augmentation bounds (i.e., the processor speed-up), that guarantees the fault tolerance feasibility, if the sufficient test fails. Finally, we prove that, if the error burst length is no more than half the shortest relative deadline of the task set, the minimum processor speed-up required to guarantee fault tolerance feasibility is upper-bounded by 6.

Supplementary Material

JPG File (p41-thekkilakattil.jpg)
EDF schedule under faults with Tlength = 4

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cover image ACM Other conferences
RTNS '12: Proceedings of the 20th International Conference on Real-Time and Network Systems
November 2012
216 pages
ISBN:9781450314091
DOI:10.1145/2392987
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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  • University of Lorraine: University of Lorraine
  • INRIA: Institut Natl de Recherche en Info et en Automatique
  • GDR ASR: GDR Architecture, Systèmes et Réseaux

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 08 November 2012

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Author Tags

  1. error bursts
  2. fault tolerance feasibility
  3. real-time scheduling
  4. resource augmentation

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RTNS '12
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  • University of Lorraine
  • INRIA
  • GDR ASR

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Overall Acceptance Rate 119 of 255 submissions, 47%

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